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* Fix misleading comments in ARMAsmParserAmaury de la Vieuville2013-06-101-6/+6
| | | | llvm-svn: 183657
* ARM: ISB cannot be passed the same options as DMBAmaury de la Vieuville2013-06-107-2/+157
| | | | | | ISB should only accepts full system sync, other options are reserved llvm-svn: 183656
* [NVPTX] Remove old CONST_NOT_GEN address space that is not being used ↵Justin Holewinski2013-06-103-39/+11
| | | | | | anymore and causes constants to be emitted in the global address space llvm-svn: 183652
* Fix a regression I introduced when I expanded the complex pseudos inReed Kotler2013-06-092-9/+10
| | | | | | | | | the Mips16 port. A few of the psuedos could either take signed or unsigned arguments and I did not distinguish the case and improperly rejected some valid cases that the assembler had previously accepted when they were pure pseudos that expanded as assembly instructions. llvm-svn: 183633
* Fix ARM unwind opcode assembler in several cases.Logan Chien2013-06-093-169/+185
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changes to ARM unwind opcode assembler: * Fix multiple .save or .vsave directives. Besides, the order is preserved now. * For the directives which will generate multiple opcodes, such as ".save {r0-r11}", the order of the unwind opcode is fixed now, i.e. the registers with less encoding value are popped first. * Fix the $sp offset calculation. Now, we can use the .setfp, .pad, .save, and .vsave directives at any order. Changes to test cases: * Add test cases to check the order of multiple opcodes for the .save directive. * Fix the incorrect $sp offset in the test case. The stack pointer offset specified in the test case was incorrect. (Changed test cases: ehabi-mc-section.ll and ehabi-mc.ll) * The opcode to restore $sp are slightly reordered. The behavior are not changed, and the new output is same as the output of GNU as. (Changed test cases: eh-directive-pad.s and eh-directive-setfp.s) llvm-svn: 183627
* Removed PackedDouble domain from scalar instructions. Added more formats for ↵Elena Demikhovsky2013-06-092-43/+60
| | | | | | the scalar stuff. llvm-svn: 183626
* Make DeadArgumentElimination more conservative on variadic functionsTim Northover2013-06-091-5/+17
| | | | | | | Variadic functions are particularly fragile in the face of ABI changes, so this limits how much the pass changes them llvm-svn: 183625
* ARM FastISel fix load register classesJF Bastien2013-06-091-4/+4
| | | | | | | | The register classes when emitting loads weren't quite restricting enough, leading to MI verification failure on the result register. These are new failures that weren't there the first time I tried enabling ARM FastISel for new targets. llvm-svn: 183624
* TargetLowering: Clean up method description commentsDavid Majnemer2013-06-081-3/+3
| | | | llvm-svn: 183623
* sys::process::get_id() now returns the process ID instead of a process ↵Aaron Ballman2013-06-081-1/+1
| | | | | | handle on Windows. Patch thanks to Kim Gräsman! llvm-svn: 183621
* [Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc ↵Venkatraman Govindaraju2013-06-087-162/+61
| | | | | | backend. llvm-svn: 183613
* ARM: fix VMOVvnf32 decoding when ambiguous with VCVTAmaury de la Vieuville2013-06-081-0/+4
| | | | | | Enforce Table A7-15 (op=1, cmode=0b111) -> UNDEF llvm-svn: 183612
* ARM: enforce SRS decoding constraintsAmaury de la Vieuville2013-06-081-1/+7
| | | | llvm-svn: 183611
* ARM: fix CPS decoding when ambiguous with QADDAmaury de la Vieuville2013-06-082-0/+34
| | | | | | | | | Handle the case when the disassembler table can't tell the difference between some encodings of QADD and CPS. Add some necessary safe guards in CPS decoding as well. llvm-svn: 183610
* ARM: fix VCVT decodingAmaury de la Vieuville2013-06-081-2/+2
| | | | | | UNPRED was reported instead of UNDEF llvm-svn: 183608
* Fix a potential bug in r183584.Shuxin Yang2013-06-081-4/+8
| | | | | | | | | | | | | r183584 tries to derive some info from the code *AFTER* a call and apply these derived info to the code *BEFORE* the call, which is not always safe as the call in question may never return, and in this case, the derived info is invalid. Thank Duncan for pointing out this potential bug. rdar://14073661 llvm-svn: 183606
* Don't artifically restrict input object size.Sean Silva2013-06-081-2/+0
| | | | | | | | sys::IdentifyFileType is already conscious of the length, and object_error::invalid_file_type is returned below anyway if sys::IdentifyFileType doesn't recognize the file. llvm-svn: 183605
* Fix unused variable warning from my previous patch.JF Bastien2013-06-081-0/+1
| | | | llvm-svn: 183601
* [mips] Use a helper function which compares the size of the source andAkira Hatanaka2013-06-082-8/+21
| | | | | | | | destination operands of an instruction. No functionality changes. llvm-svn: 183596
* Reapply r183552. This time, use a standard type for the option to avoid templateQuentin Colombet2013-06-081-0/+13
| | | | | | | | | | | | | | | instantiation issue with non-standard type. Add a backend option to warn on a given stack size limit. Option: -mllvm -warn-stack-size=<limit> Output (if limit is exceeded): warning: Stack size limit exceeded (<actual size>) in <functionName>. The longer term plan is to hook that to a clang warning. PR:4072 <rdar://problem/13987214>. llvm-svn: 183595
* R600: Use a refined heuristic to choose when switching clauseVincent Lejeune2013-06-072-10/+47
| | | | | | | | | | | | | | | This is using a hint from AMD APP OpenCL Programming Guide with empirically tweaked parameters. I used Unigine Heaven 3.0 to determine best parameters on my system (i7 2600/Radeon 6950/Kernel 3.9.4) the benchmark : it went from 38.8 average fps to 39.6, which is ~3% gain. (Lightmark 2008.2 gain is much more marginal: from 537 to 539) There is no lit test provided as the parameter were determined empirically and it it would be nearly impossiblet to find a test program that check for optimal behavior. llvm-svn: 183593
* R600: Anti dep better handled in tex clauseVincent Lejeune2013-06-071-6/+4
| | | | llvm-svn: 183592
* Remember the anyext patterns.Jakob Stoklund Olesen2013-06-071-0/+2
| | | | llvm-svn: 183589
* Add missing zextloadi1 to i64 patterns. PR16721.Jakob Stoklund Olesen2013-06-071-0/+3
| | | | llvm-svn: 183587
* Fix an assertion in MemCpyOpt pass.Shuxin Yang2013-06-071-2/+4
| | | | | | | | | | | | | | | | | | | | | The MemCpyOpt pass is capable of optimizing: callee(&S); copy N bytes from S to D. into: callee(&D); subject to some legality constraints. Assertion is triggered when the compiler tries to evalute "sizeof(typeof(D))", while D is an opaque-typed, 'sret' formal argument of function being compiled. i.e. the signature of the func being compiled is something like this: T caller(...,%opaque* noalias nocapture sret %D, ...) The fix is that when come across such situation, instead of calling some utility functions to get the size of D's type (which will crash), we simply assume D has at least N bytes as implified by the copy-instruction. rdar://14073661 llvm-svn: 183584
* Disallow i64 div/rem in PPC32 counter loopsHal Finkel2013-06-071-0/+7
| | | | | | | | On PPC32, [su]div,rem on i64 types are transformed into runtime library function calls. As a result, they are not allowed in counter-based loops (the counter-loops verification pass caught this error; this change fixes PR16169). llvm-svn: 183581
* Revert commits related to stack warning.Quentin Colombet2013-06-071-13/+0
| | | | llvm-svn: 183579
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-073-6/+6
| | | | | | | | the internals of TargetMachine could change. No functionality change intended. llvm-svn: 183572
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-077-16/+33
| | | | | | | | the internals of TargetMachine could change. No functionality change intended. llvm-svn: 183571
* Remove unused c'tor.Bill Wendling2013-06-071-7/+2
| | | | llvm-svn: 183570
* R600: Fix calculation of stack offset in AMDGPUFrameLoweringTom Stellard2013-06-071-21/+2
| | | | | | | | | We weren't computing structure size correctly and we were relying on the original alloca instruction to compute the offset, which isn't always reliable. Reviewed-by: Vincent Lejeune <vljn@ovi.com> llvm-svn: 183568
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-074-8/+10
| | | | | | | | the internals of TargetMachine could change. No functionality change intended. llvm-svn: 183567
* R600: Rework subtarget info and remove AMDILDevice classesTom Stellard2013-06-0736-1458/+218
| | | | | | | | This should simplify the subtarget definitions and make it easier to add new ones. Reviewed-by: Vincent Lejeune <vljn@ovi.com> llvm-svn: 183566
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-074-9/+10
| | | | | | | | the internals of TargetMachine could change. No functionality change intended. llvm-svn: 183565
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-0721-63/+75
| | | | | | | | the internals of TargetMachine could change. No functionality change intended. llvm-svn: 183561
* R600: Fix the fetch limits for R600 generation GPUsTom Stellard2013-06-074-27/+30
| | | | | | | | Reviewed-by: Vincent Lejeune <vljn@ovi.com> https://bugs.freedesktop.org/show_bug.cgi?id=64257 llvm-svn: 183560
* R600: Move Subtarget feature definitions into AMDGPU.tdTom Stellard2013-06-072-64/+66
| | | | | | | This is the convention used by the other targets. Reviewed-by: Vincent Lejeune <vljn@ovi.com> llvm-svn: 183559
* R600: Remove unnecessary includeTom Stellard2013-06-073-2/+4
| | | | | Reviewed-by: Vincent Lejeune <vljn@ovi.com> llvm-svn: 183558
* Add a backend option to warn on a given stack size limit.Quentin Colombet2013-06-071-0/+13
| | | | | | | | | | | | Option: -mllvm -warn-stack-size=<limit> Output (if limit is exceeded): warning: Stack size limit exceeded (<actual size>) in <functionName>. The longer term plan is to hook that to a clang warning. PR:4072 <rdar://problem/13987214> llvm-svn: 183552
* ARM FastISel integer sext/zext improvementsJF Bastien2013-06-071-38/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | My recent ARM FastISel patch exposed this bug: http://llvm.org/bugs/show_bug.cgi?id=16178 The root cause is that it can't select integer sext/zext pre-ARMv6 and asserts out. The current integer sext/zext code doesn't handle other cases gracefully either, so this patch makes it handle all sext and zext from i1/i8/i16 to i8/i16/i32, with and without ARMv6, both in Thumb and ARM mode. This should fix the bug as well as make FastISel faster because it bails to SelectionDAG less often. See fastisel-ext.patch for this. fastisel-ext-tests.patch changes current tests to always use reg-imm AND for 8-bit zext instead of UXTB. This simplifies code since it is supported on ARMv4t and later, and at least on A15 both should perform exactly the same (both have exec 1 uop 1, type I). 2013-05-31-char-shift-crash.ll is a bitcode version of the above bug 16178 repro. fast-isel-ext.ll tests all sext/zext combinations that ARM FastISel should now handle. Note that my ARM FastISel enabling patch was reverted due to a separate failure when dealing with MCJIT, I'll fix this second failure and then turn FastISel on again for non-iOS ARM targets. I've tested "make check-all" on my x86 box, and "lnt test-suite" on A15 hardware. llvm-svn: 183551
* R600: Don't compare iterators of different maps.Benjamin Kramer2013-06-071-1/+1
| | | | | | Found be libstdc's debug mode. llvm-svn: 183549
* Teach AsmPrinter how to print odd constants.Quentin Colombet2013-06-071-2/+43
| | | | | | | | | | | Fix an assertion when the compiler encounters big constants whose bit width is not a multiple of 64-bits. Although clang would never generate something like this, the backend should be able to handle any legal IR. <rdar://problem/13363576> llvm-svn: 183544
* DIBuilder: No functionality change.Manman Ren2013-06-071-23/+26
| | | | | | Use the correct DIType when creating types in DIBuilder. llvm-svn: 183543
* Vincent says the element is at most once in the vector, so we don't need a ↵Benjamin Kramer2013-06-071-3/+7
| | | | | | full std::remove. llvm-svn: 183541
* Use isxdigit.Rafael Espindola2013-06-071-9/+1
| | | | | | Thanks to Benjamin Kramer for the suggestion. llvm-svn: 183540
* Fix a typo in asm string of BP* family of instructions. With this fixRoman Divacky2013-06-071-1/+1
| | | | | | I am able to compile/assemble/link/run /bin/echo from FreeBSD. llvm-svn: 183537
* Support OpenBSD's native frame protection conventions.Rafael Espindola2013-06-071-11/+36
| | | | | | | | | | | | | | | OpenBSD's stack smashing protection differs slightly from other platforms: 1. The smash handler function is "__stack_smash_handler(const char *funcname)" instead of "__stack_chk_fail(void)". 2. There's a hidden "long __guard_local" object that gets linked into each executable and DSO. Patch by Matthew Dempsky. llvm-svn: 183533
* R600: Fix a potential iterator invalidation issue.Benjamin Kramer2013-06-071-5/+3
| | | | | | As a bonus this reduces the loop from O(n^2) to O(n). llvm-svn: 183532
* R600: Remove an extra break in R600OptimizeVectorRegisters.cppVincent Lejeune2013-06-071-3/+1
| | | | llvm-svn: 183528
* Fold variable that's only used in assert into the assert.Benjamin Kramer2013-06-071-2/+1
| | | | | | Avoids unused variable warnings in Release builds. llvm-svn: 183512
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