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* [X86] Use alignTo and divideCeil to make some code more readable. NFCCraig Topper2018-07-281-3/+3
| | | | llvm-svn: 338203
* [InstCombine] try to fold 'sub' to 'not'Sanjay Patel2018-07-281-1/+7
| | | | | | | | | | | https://rise4fun.com/Alive/jDd Patterns with add/sub combos can be improved using 'not' ops. This is better for analysis and may lead to follow-on transforms because 'xor' and 'add' are commutative/associative. It can also help codegen. llvm-svn: 338200
* [AArch64][SVE] Asm: Support for PFALSE and PTEST instructions.Sander de Smalen2018-07-282-0/+45
| | | | | | | | This patch adds PFALSE (unconditionally sets all elements of the predicate to false) and PTEST (set the status flags for the predicate). llvm-svn: 338198
* AMDGPU: Stop wasting argument registers with v3i32/v3f32Matt Arsenault2018-07-282-0/+59
| | | | | | | | | | SelectionDAGBuilder widens v3i32/v3f32 arguments to to v4i32/v4f32 which consume an additional register. In addition to wasting argument space, this produces extra instructions since now it appears the 4th vector component has a meaningful value to most combines. llvm-svn: 338197
* [AArch64][SVE] Asm: Data-dependent loop predicate partitioning instructions.Sander de Smalen2018-07-282-0/+100
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for instructions that partition a predicate based on data-dependent termination conditions in a loop. BRKA Break after the first true condition BRKAS Break after the first true condition, setting condition flags BRKB Break before the first true condition BRKBS Break before the first true condition, setting condition flags BRKPA Break after the first true condition, propagating from the previous partition BRKPAS Break after the first true condition, propagating from the previous partition, setting condition flags BRKPB Break before the first true condition, propagating from the previous partition BRKPBS Break before the first true condition, propagating from the previous partition, setting condition flags BRKN Propagate break to next partition BKRNS Propagate break to next partition, setting condition flags llvm-svn: 338196
* DAG: Add calling convention argument to calling convention funcsMatt Arsenault2018-07-2819-124/+159
| | | | | | | | This seems like a pretty glaring omission, and AMDGPU wants to treat kernels differently from other calling conventions. llvm-svn: 338194
* AMDGPU: Stop trying to extend arguments for cloverMatt Arsenault2018-07-282-31/+1
| | | | | | | This was trying to replace i8/i16 arguments with i32, which was broken and no longer necessary. llvm-svn: 338193
* [GlobalOpt] Test array indices inside structs for out-of-bounds accessesDavid Green2018-07-281-71/+47
| | | | | | | | | | | | | | | | | | We now, from clang, can turn arrays of static short g_data[] = {16, 16, 16, 16, 16, 16, 16, 16, 0, 0, 0, 0, 0, 0, 0, 0}; into structs of the form @g_data = internal global <{ [8 x i16], [8 x i16] }> ... GlobalOpt will incorrectly SROA it, not realising that the access to the first element may overflow into the second. This fixes it by checking geps more thoroughly. I believe this makes the globalsra-partial.ll test case invalid as the %i value could be out of bounds. I've re-purposed it as a negative test for this case. Differential Revision: https://reviews.llvm.org/D49816 llvm-svn: 338192
* [InstCombine] Fold Select with AND/OR conditionDavid Bolvansky2018-07-281-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Fold ``` %A = icmp ne i8 %X, %V1 %B = icmp ne i8 %X, %V2 %C = or i1 %A, %B %D = select i1 %C, i8 %X, i8 %V1 ret i8 %D => ret i8 %X Fixes https://bugs.llvm.org/show_bug.cgi?id=38334 Proof: https://rise4fun.com/Alive/plI8 Reviewers: spatel, lebedev.ri Reviewed By: lebedev.ri Subscribers: craig.topper, llvm-commits Differential Revision: https://reviews.llvm.org/D49919 llvm-svn: 338191
* [demangler] Fix an oss-fuzz bug from r338138Erik Pilkington2018-07-281-0/+8
| | | | | | | | Stack overflow on invalid. While collapsing references, we were skipping over a cycle check in ForwardTemplateReference leading to a stack overflow. This commit fixes the problem by duplicating the cycle check in ReferenceType. llvm-svn: 338190
* [DAGCombiner] Teach DAG combiner that A-(B-C) can be folded to A+(C-B)Craig Topper2018-07-281-0/+6
| | | | | | | | This can be useful since addition is commutable, and subtraction is not. This matches a transform that is also done by InstCombine. llvm-svn: 338181
* [SimpleLoopUnswitch] Fix DT updates for trivial branch unswitching.Alina Sbirlea2018-07-281-2/+4
| | | | | | | | | | | | | | | Summary: Fixing 2 issues with the DT update in trivial branch switching, though I don't have a case where DT update fails. 1. After splitting ParentBB->UnswitchedBB edge, new edges become: ParentBB->LoopExitBB->UnswitchedBB, so remove ParentBB->LoopExitBB edge. 2. AFAIU, for multiple CFG changes, DT should be updated using batch updates, vs consecutive addEdge and removeEdge calls. Reviewers: chandlerc, kuhar Subscribers: sanjoy, jlebar, llvm-commits Differential Revision: https://reviews.llvm.org/D49925 llvm-svn: 338180
* Revert "[WebAssembly] Added default stack-only instruction mode for MC."Wouter van Oortmerssen2018-07-275-475/+252
| | | | | | | This reverts commit d3c9af4179eae7793d1487d652e2d4e23844555f. (SVN revision 338164) llvm-svn: 338176
* [Support] Remove unnecessary MemoryBuffer::anchor (where the destructor ↵Fangrui Song2018-07-271-2/+1
| | | | | | serves as the key function) llvm-svn: 338175
* [X86] Add support expanding multiplies by constant where the constant is ↵Craig Topper2018-07-271-18/+31
| | | | | | | | -3/-5/-9 multplied by a power of 2. These can be replaced with an LEA, a shift, and a negate. This seems to match what gcc and icc would do. llvm-svn: 338174
* [InstrProf] Don't register __llvm_profile_runtime_userReid Kleckner2018-07-271-1/+1
| | | | | | | | Refactor some FileCheck prefixes while I'm at it. Fixes PR38340 llvm-svn: 338172
* [WebAssembly] Added default stack-only instruction mode for MC.Wouter van Oortmerssen2018-07-275-252/+475
| | | | | | | | | | | | | | | | | | | | | | | Summary: Moved Explicit Locals pass to last. Made that pass obligatory. Made it convert from register to stack based instructions, and removed the registers. Fixes to related code that was expecting register based instructions. Added the correct testing flag to all tests, depending on what the format they were expecting so far. Translated one test to stack format as example: reg-stackify-stack.ll tested: llvm-lit -v `find test -name WebAssembly` unittests/MC/* Reviewers: dschuff, sunfish Subscribers: sbc100, jgravelle-google, eraman, aheejin, llvm-commits Differential Revision: https://reviews.llvm.org/D49160 llvm-svn: 338164
* Recommit "Enable MachineOutliner by default under -Oz for AArch64"Jessica Paquette2018-07-273-0/+9
| | | | | | | | | | | | | | | | | | Fixed the ASAN failure from before in r338148, so recommiting. This patch enables the MachineOutliner by default in AArch64 under -Oz. The MachineOutliner offers around a 4.5% improvement on the current -Oz code size improvements. We have done work into improving the debuggability of outlined code, so that users of -Oz won't be surprised by the optimization. We have also been executing the LLVM test suite and common external tests such as the SPEC suites continuously with no issue. The outliner has a low compile-time overhead of roughly 1%. At this point, the outliner would be a really good addition to the -Oz pass pipeline! llvm-svn: 338160
* [MachineOutliner] Exit getOutliningCandidateInfo when we erase all candidatesJessica Paquette2018-07-272-1/+11
| | | | | | | | | | There was a missing check for if a candidate list was entirely deleted. This adds that check. This fixes an asan failure caused by running test/CodeGen/AArch64/addsub_ext.ll with the MachineOutliner enabled. llvm-svn: 338148
* [ARM] Add new target feature to fuse literal generationEvandro Menezes2018-07-273-19/+55
| | | | | | | | | | This feature enables the fusion of such operations on Cortex A57 and Cortex A72, as recommended in their Software Optimisation Guides, sections 4.14 and 4.11, respectively. Differential revision: https://reviews.llvm.org/D49563 llvm-svn: 338147
* [demangler] Support for reference collapsingErik Pilkington2018-07-271-46/+56
| | | | | | llvm.org/PR38323 llvm-svn: 338138
* Revert "Enable MachineOutliner by default under -Oz for AArch64"Jessica Paquette2018-07-273-9/+0
| | | | | | | | | | It failed an Asan test on a bot: http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/21543/steps/check-llvm%20asan/logs/stdio Fixing that before recommitting. llvm-svn: 338136
* bpf: add missing RegState to notify MachineInstr verifier necessary register ↵Yonghong Song2018-07-271-8/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | usage Errors like the following are reported by: https://urldefense.proofpoint.com/v2/url?u=http-3A__lab.llvm.org-3A8011_builders_llvm-2Dclang-2Dx86-5F64-2Dexpensive-2Dchecks-2Dwin_builds_11261&d=DwIBAg&c=5VD0RTtNlTh3ycd41b3MUw&r=DA8e1B5r073vIqRrFz7MRA&m=929oWPCf7Bf2qQnir4GBtowB8ZAlIRWsAdTfRkDaK-g&s=9k-wbEUVpUm474hhzsmAO29VXVvbxJPWD9RTgCD71fQ&e= *** Bad machine code: Explicit definition marked as use *** - function: cal_align1 - basic block: %bb.0 entry (0x47edd98) - instruction: LDB $r3, $r2, 0 - operand 0: $r3 This is because RegState info was missing for ScratchReg inside expandMEMCPY. This caused incomplete register usage information to MachineInstr verifier which then would complain as there could be potential code-gen issue if the complained MachineInstr is used in place where register usage information matters even though the memcpy expanding is not in such case as it happens at the last stage of IR optimization pipeline. We should always specify those register usage information which compiler couldn't deduct automatically whenever we add a hardware register manually. Reported-by: Builder llvm-clang-x86_64-expensive-checks-win Build #11261 Signed-off-by: Jiong Wang <jiong.wang@netronome.com> Reviewed-by: Yonghong Song <yhs@fb.com> llvm-svn: 338134
* Enable MachineOutliner by default under -Oz for AArch64Jessica Paquette2018-07-273-0/+9
| | | | | | | | | | | | | | | | This patch enables the MachineOutliner by default in AArch64 under -Oz. The MachineOutliner offers around a 4.5% improvement on the current -Oz code size improvements. We have done work into improving the debuggability of outlined code, so that users of -Oz won't be surprised by the optimization. We have also been executing the LLVM test suite and common external tests such as the SPEC suites continuously with no issue. The outliner has a low compile-time overhead of roughly 1%. At this point, the outliner would be a really good addition to the -Oz pass pipeline! llvm-svn: 338133
* [DAGCombiner] fold 'not' with signbit mathSanjay Patel2018-07-271-0/+45
| | | | | | | | | | | | | | | | | | | This is a follow-up suggested in D48970. Alive proofs: https://rise4fun.com/Alive/sII We can eliminate an instruction in the usual select-of-constants to bit hack transform by adjusting the add/sub with constant. This is always a win. There are more transforms that are likely wins, but they may need target hooks in case some targets do not benefit. This is another step towards making up for canonicalizing to select-of-constants in rL331486. llvm-svn: 338132
* [Support] Use unsigned char for xxHash 64-bitFangrui Song2018-07-271-3/+3
| | | | | | Before, the last 3 bytes were char-signedness dependent. llvm-svn: 338128
* AMDGPU/R600: Add MOV instructions to BFE patternsJan Vesely2018-07-271-5/+5
| | | | | | | | | R600 can't handle immediates for BFE, these will be eliminated later. Fixes powr/pow regressions n r600 since r334817 Differential Revision: https://reviews.llvm.org/D49641 llvm-svn: 338127
* [AArch64][SVE] Asm: Predicated integer reductions.Sander de Smalen2018-07-272-0/+62
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for various integer reduction operations: SADDV signed add reduction to scalar UADDV unsigned add reduction to scalar SMAXV signed maximum reduction to scalar SMINV signed minimum reduction to scalar UMAXV unsigned maximum reduction to scalar UMINV unsigned minimum reduction to scalar ANDV logical AND reduction to scalar ORV logical OR reduction to scalar EORV logical EOR reduction to scalar The reduction is predicated, e.g. smaxv s0, p0, z1.s performs a signed maximum reduction on active elements in z1, and stores the (signed max value) result in s0. llvm-svn: 338126
* [AArch64][SVE] Asm: Predicated floating point reductions.Sander de Smalen2018-07-272-1/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for various floating-point reduction operations: FADDA strictly-ordered add reduction, accumulating in scalar FADDV recursive add reduction to scalar FMAXV recursive max reduction to scalar FMINV recursive min reduction to scalar FMAXNMV recursive max number reduction to scalar FMINNMV recursive min number reduction to scalar The reduction is predicated, e.g. fadda d0, p0, d0, z1.d performs the add-reduction in strict order on active elements in z1, accumulating into d0. faddv d0, p0, z1.d performs the add-reduction (not in strict order) on active elements in z1, storing the result in d0. llvm-svn: 338123
* [AArch64][SVE] Asm: Support for FEXPA and FTSSEL.Sander de Smalen2018-07-272-0/+51
| | | | | | | | This patch adds support for transcendental acceleration instructions 'FEXPA' (exponential accelerator) and 'FTSSEL' (trigonometric select coefficient). llvm-svn: 338121
* [AArch64][SVE] Asm: Support for FRECPE and FRSQRTE.Sander de Smalen2018-07-272-0/+30
| | | | | | | Support for floating-point instructions for reciprocal estimate (FRECPE) and reciprocal square root estimate (FRSQRTE). llvm-svn: 338120
* [InstCombine] not(sub X, Y) --> add (not X), YSanjay Patel2018-07-271-0/+4
| | | | | | | | | | | The tests with constants show a missing optimization. Analysis for adds is better than subs, so this can also help with other transforms. And codegen is better with adds for targets like x86 (destructive ops, no sub-from). https://rise4fun.com/Alive/llK llvm-svn: 338118
* [SimplifyIndVar] Canonicalize comparisons to unsigned while eliminating truncsMax Kazantsev2018-07-271-2/+23
| | | | | | | | | | | This is a follow-up for the patch rL335020. When we replace compares against trunc with compares against wide IV, we can also replace signed predicates with unsigned where it is legal. Reviewed By: reames Differential Revision: https://reviews.llvm.org/D48763 llvm-svn: 338115
* AMDGPU: Fix code size for return_to_epilog pseudoMatt Arsenault2018-07-272-3/+4
| | | | llvm-svn: 338113
* DAG: Remove unnecessary .str()Matt Arsenault2018-07-271-1/+1
| | | | llvm-svn: 338112
* PatternMatch: Add wrappers for fabs and canonicalizeMatt Arsenault2018-07-271-3/+3
| | | | llvm-svn: 338111
* Revert "[LV][DebugInfo] Set DL to the middle block Icmp instruction"Anastasis Grammenos2018-07-271-3/+1
| | | | | | This reverts commit r338106. llvm-svn: 338109
* [LV][DebugInfo] Set DL to the middle block Icmp instructionAnastasis Grammenos2018-07-271-1/+3
| | | | | | | | Reviewers: hsaito Differential Revision: https://reviews.llvm.org/D49746 llvm-svn: 338106
* [NFC] Remove an empty line.Xin Tong2018-07-271-1/+0
| | | | llvm-svn: 338104
* AMDGPU/GlobalISel: Fix crash in regbankselect on non-power-of-2 typesTom Stellard2018-07-271-1/+1
| | | | | | | | | | | | Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D49624 llvm-svn: 338102
* [X86] Remove an unnecessary 'if' that prevented treating INT64_MAX and ↵Craig Topper2018-07-271-38/+36
| | | | | | | | -INT64_MAX as power of 2 minus 1 in the multiply expansion code. Not sure why they were being explicitly excluded, but I believe all the math inside the if works. I changed the absolute value to be uint64_t instead of int64_t so INT64_MIN+1 wouldn't be signed wrap. llvm-svn: 338101
* [LTO] Don't internalize declarationsBob Haarman2018-07-271-1/+2
| | | | | | | | | | | | | | | | | | | | Summary: Some links were failing with "Global is external, but doesn't have external or weak linkage!" in ThinLTO builds with debug information. This happened when we elide the body of a global that is referenced by debug info. This results in a declaration, which we would then internalize - but declarations cannot be internal. This change avoids the problem by not internalizing these declarations. Fixes PR38046. Reviewers: pcc, tejohnson Subscribers: mehdi_amini, aprantl, hiraditya, JDevlieghere, steven_wu, dexonsmith, llvm-commits Differential Revision: https://reviews.llvm.org/D49777 llvm-svn: 338100
* Replace LLVM_ALIGNAS with alignas as a follow-up of r337330Fangrui Song2018-07-271-1/+1
| | | | | | The minimum required GCC version was raised to 4.8 (which started to support alignas) in r284497. llvm-svn: 338099
* [X86] Add matching for another pattern of PMADDWD.Craig Topper2018-07-271-0/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is the pattern you get from the loop vectorizer for something like this int16_t A[1024]; int16_t B[1024]; int32_t C[512]; void pmaddwd() { for (int i = 0; i != 512; ++i) C[i] = (A[2*i]*B[2*i]) + (A[2*i+1]*B[2*i+1]); } In this case we will have (add (mul (build_vector), (build_vector)), (mul (build_vector), (build_vector))). This is different than the pattern we currently match which has the build_vectors between an add and a single multiply. I'm not sure what C code would get you that pattern. Reviewers: RKSimon, spatel, zvi Reviewed By: zvi Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D49636 llvm-svn: 338097
* [InstCombine] canonicalize abs patternChen Zheng2018-07-271-20/+50
| | | | | | Differential Revision: https://reviews.llvm.org/D48754 llvm-svn: 338092
* [X86] When removing sign extends from gather/scatter indices, make sure we ↵Craig Topper2018-07-271-15/+20
| | | | | | | | handle UpdateNodeOperands finding an existing node to CSE with. If this happens the operands aren't updated and the existing node is returned. Make sure we pass this existing node up to the DAG combiner so that a proper replacement happens. Otherwise we get stuck in an infinite loop with an unoptimized node. llvm-svn: 338090
* [SelectionDAGBuilder] Add masked loads to PendingLoads rather than calling ↵Craig Topper2018-07-261-4/+2
| | | | | | | | | | DAG.setRoot. Masked loads are calling DAG.getRoot rather than calling SelectionDAGBuilder::getRoot, which means the PendingLoads weren't emptied to update the root and create any needed TokenFactor. So it would be incorrect to call setRoot for the masked load. This patch instead adds the masked load to PendingLoads so that the root doesn't get update until a store or scatter or something happens.. Alternatively, we could call SelectionDAGBuilder::getRoot before it, but that would create unnecessary serialization. llvm-svn: 338085
* [InstrProf] Use comdats on COFF for available_externally functionsReid Kleckner2018-07-261-2/+1
| | | | | | | | | | | | | | | | | | | Summary: r262157 added ELF-specific logic to put a comdat on the __profc_* globals created for available_externally functions. We should be able to generalize that logic to all object file formats that support comdats, i.e. everything other than MachO. This fixes duplicate symbol errors, since on COFF, linkonce_odr doesn't make the symbol weak. Fixes PR38251. Reviewers: davidxl, xur Subscribers: hiraditya, dmajor, llvm-commits, aheejin Differential Revision: https://reviews.llvm.org/D49882 llvm-svn: 338082
* [DWARF v5] Reposting r337981, which was reverted in r337997 due to a test ↵Wolfgang Pieb2018-07-263-51/+41
| | | | | | | | | failure in debuginfo_tests. The test failure was caused by the compiler not emitting a __debug_ranges section with DWARF 4 and earlier when no ranges are needed. The test checks for the existence regardless. llvm-svn: 338081
* [SelectionDAG] Add MLOAD/MSTORE/MGATHER/MSCATTER to AddNodeIDCustom to ↵Craig Topper2018-07-261-0/+28
| | | | | | properly calculate their folding set ID to allow them to be CSEd. llvm-svn: 338080
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