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* [X86] Cleanup 'x' and 'y' mnemonic suffixes for ↵Craig Topper2016-11-143-23/+71
| | | | | | | | | | | | | vcvtpd2dq/vcvttpd2dq/vcvtpd2ps and similar instructions. -Don't print the 'x' suffix for the 128-bit reg/mem VEX encoded instructions in Intel syntax. This is consistent with the EVEX versions. -Don't print the 'y' suffix for the 256-bit reg/reg VEX encoded instructions in Intel or AT&T syntax. This is consistent with the EVEX versions. -Allow the 'x' and 'y' suffixes to be used for the reg/mem forms when we're assembling using Intel syntax. -Allow the 'x' and 'y' suffixes on the reg/reg EVEX encoded instructions in Intel or AT&T syntax. This is consistent with what VEX was already allowing. This should fix at least some of PR28850. llvm-svn: 286787
* [AVX-512] Remove and autoupgrade masked dword/qword variable shift ↵Craig Topper2016-11-142-32/+35
| | | | | | intrinsics to the new unmasked versions and selects. llvm-svn: 286786
* [ValueTracking] recognize even more variants of smin/smaxSanjay Patel2016-11-131-0/+20
| | | | | | | | | | | | | | | | Similar to: https://reviews.llvm.org/rL285499 https://reviews.llvm.org/rL286318 We can't minimally expose this in IR tests because we don't have min/max intrinsics, but the difference is visible in codegen because SelectionDAGBuilder::visitSelect() uses matchSelectPattern(). We're not canonicalizing these patterns in IR (yet), so I don't expect there to be any regressions as noted here: http://lists.llvm.org/pipermail/llvm-dev/2016-November/106868.html llvm-svn: 286776
* [AVX-512] Fix a disassembler failure for AVX-512 vcmpss/vcmpsd with an ↵Craig Topper2016-11-131-4/+14
| | | | | | | | immediate larger than 32. Fix the same bug with VLX vcmpps/vcmppd. Fixes PR24941. llvm-svn: 286775
* [ValueTracking] move min/max matching to helper function; NFCISanjay Patel2016-11-131-46/+59
| | | | llvm-svn: 286772
* [X86][IR] Reduce the number of full string comparisons in the code that ↵Craig Topper2016-11-131-156/+173
| | | | | | autoupgrades masked shift intrinsics. llvm-svn: 286768
* AMDGPU: Implement SGPR spilling with scalar storesMatt Arsenault2016-11-133-10/+153
| | | | | | | | | | | | | | | | nThis avoids the nasty problems caused by using memory instructions that read the exec mask while spilling / restoring registers used for control flow masking, but only for VI when these were added. This always uses the scalar stores when enabled currently, but it may be better to still try to spill to a VGPR and use this on the fallback memory path. The cache also needs to be flushed before wave termination if a scalar store is used. llvm-svn: 286766
* revert commit r286761, some builds failed on Win platformsIgor Breger2016-11-132-17/+4
| | | | llvm-svn: 286765
* [X86][AVX512] Removing llvm x86 intrinsics for _mm_mask_move_{ss|sd} intrinsics.Ayman Musa2016-11-132-4/+17
| | | | | | Differential Revision: https://reviews.llvm.org/D26128 llvm-svn: 286761
* [X86][AVX512] Add patterns for all variants of VMOVSS/VMOVSD instructions.Ayman Musa2016-11-132-0/+91
| | | | | | Differential Revision: https://reviews.llvm.org/D26022 llvm-svn: 286758
* [InstCombine][AVX-512] Teach InstCombineCalls to handle the new unmasked ↵Craig Topper2016-11-131-4/+18
| | | | | | AVX-512 variable shift intrinsics. llvm-svn: 286755
* [AVX-512] Add unmasked intrinsics for variable shifts of dwords and qwords.Craig Topper2016-11-131-0/+8
| | | | | | These will be used to replace the masked intrinsics so that InstCombineCalls can optimize the AVX-512 variable shifts the same way it does for AVX2. llvm-svn: 286754
* [AMDGPU] Add f16 support (VI+)Konstantin Zhuravlyov2016-11-1318-238/+617
| | | | | | Differential Revision: https://reviews.llvm.org/D25975 llvm-svn: 286753
* Bitcode: Change module reader functions to return an llvm::Expected.Peter Collingbourne2016-11-1310-103/+77
| | | | | | Differential Revision: https://reviews.llvm.org/D26562 llvm-svn: 286752
* Analysis: Simplify the ScalarEvolution::getGEPExpr() interface. NFCI.Peter Collingbourne2016-11-133-14/+10
| | | | | | | | All existing callers were manually extracting information out of an existing GEP instruction and passing it to getGEPExpr(). Simplify the interface by changing it to take a GEPOperator instead. llvm-svn: 286751
* Bitcode: More precise casting. NFCI.Peter Collingbourne2016-11-131-3/+3
| | | | llvm-svn: 286750
* IR: Change the Type::get{Array,Vector,Pointer}ElementType() functions to ↵Peter Collingbourne2016-11-131-1/+2
| | | | | | | | perform the correct type assertion. Previously we were only asserting that the type was a sequential type. llvm-svn: 286749
* [InstCombine][AVX-512] Expand vector shift handling to work on the AVX-512 ↵Craig Topper2016-11-131-1/+45
| | | | | | | | shift by immediate and shift by single value. This does not include support for the AVX-512 variable shifts. That will be coming in a future patch. llvm-svn: 286739
* [AVX-512] Remove the remaining masked shift by immediate or by single value. ↵Craig Topper2016-11-122-77/+84
| | | | | | | | Autoupgrade them to recently introduced unmasked versions and a select. After this I'll add the unmasked intrinsics to InstCombineCalls to finish making our handling of these types of shuffles consistent between AVX-512 and the legacy intrinsics. llvm-svn: 286725
* [Support] Add StringRef::find_lower and contains_lower.Zachary Turner2016-11-121-0/+39
| | | | | | Differential Revision: https://reviews.llvm.org/D25299 llvm-svn: 286724
* [AVX-512] Add unmasked version of shift by immediate and shift by single ↵Craig Topper2016-11-121-0/+22
| | | | | | | | | | | | | | | | | | | element in XMM. Summary: This is the first step towards being able to add the avx512 shift by immediate intrinsics to InstCombineCalls where we aleady support the sse2 and avx2 intrinsics. We need to the unmasked versions so we can avoid having to teach InstCombineCalls that it would need to insert selects sometimes. Instead we'll just add the selects around the new instrinsics in the frontend. This change should also enable the shift by i32 intrinsics to take a non-constant shift value just like the avx2 and sse intrinsics. This will enable us to fix PR30691 once we update clang. Next I'll switch clang to use the new builtins. Then we'll come back to the backend and remove/autoupgrade the old intrinsics. Then I'll work on the same series for variable shifts. Reviewers: RKSimon, zvi, delena Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D26333 llvm-svn: 286711
* [AVX-512] Add support for lowering shuffles to VALIGND/VALIGNQCraig Topper2016-11-121-28/+96
| | | | | | | | | | | | Summary: VALIGND and VALIGNQ are similar to PALIGNR but instead of working on a 128-bit lane they work on the entire vector register. This change leverages the shuffle rotate detection code used for PALIGNR to detect these cases. Reviewers: delena, RKSimon Subscribers: Farhana, llvm-commits Differential Revision: https://reviews.llvm.org/D26297 llvm-svn: 286709
* [C API] Fix several null pointer dereferences.whitequark2016-11-121-0/+8
| | | | llvm-svn: 286704
* [libFuzzer] use a valid ASCII string for a dummy seed corpusKostya Serebryany2016-11-121-1/+1
| | | | llvm-svn: 286702
* [libFuzzer] use less stackKostya Serebryany2016-11-122-16/+18
| | | | llvm-svn: 286689
* Remove extra semicolon.Rui Ueyama2016-11-121-1/+1
| | | | llvm-svn: 286688
* AMDGPU/SI: Promote i16 = fp_[us]int f32 for VITom Stellard2016-11-121-0/+6
| | | | | | | | | | | | Summary: This fixes a regression caused by r286464. Reviewers: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye Differential Revision: https://reviews.llvm.org/D26570 llvm-svn: 286687
* Fix -Werror build with clang-cl.Zachary Turner2016-11-111-1/+1
| | | | llvm-svn: 286683
* [Support] Introduce llvm::formatv() function.Zachary Turner2016-11-114-28/+213
| | | | | | | | | | | | | | | | | | This introduces a new type-safe general purpose formatting library. It provides compile-time type safety, does not require a format specifier (since the type is deduced), and provides mechanisms for extending the format capability to user defined types, and overriding the formatting behavior for existing types. This patch additionally adds documentation for the API to the LLVM programmer's manual. Mailing List Thread: http://lists.llvm.org/pipermail/llvm-dev/2016-October/105836.html Differential Revision: https://reviews.llvm.org/D25587 llvm-svn: 286682
* Define DbiStreamBuilder::addSectionContribs.Rui Ueyama2016-11-111-3/+40
| | | | | | | | | | | | | | This patch defines a new function to add a SectionContribs stream to a PDB file. Unlike SectionMap, SectionContribs contains a list of input sections as opposed to output sections. Note that this patch needs improving because currently we do not set Module field in SectionContribs entries. In a follow-up patch, I'll add Modules and then fix it after that. Differential Revision: https://reviews.llvm.org/D26210 llvm-svn: 286677
* AMDGPU/SI: Fix visit order assumption in SIFixSGPRCopiesTom Stellard2016-11-111-24/+44
| | | | | | | | | | | | | | | | | | | | Summary: This pass was assuming that when a PHI instruction defined a register used by another PHI instruction that the defining insstruction would be legalized before the using instruction. This assumption was causing the pass to not legalize some PHI nodes within divergent flow-control. This fixes a bug that was uncovered by r285762. Reviewers: nhaehnle, arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D26303 llvm-svn: 286676
* [InstCombine] use dyn_cast rather isa+cast; NFCSanjay Patel2016-11-111-2/+2
| | | | | | Follow-up to r286664 cleanup as suggested by Eli. Thanks! llvm-svn: 286671
* [libFuzzer] do not initialize parts of TracePC -- let them be initialized by ↵Kostya Serebryany2016-11-112-2/+5
| | | | | | the linker. Add no-msan attribute to the memcmp hook. llvm-svn: 286665
* [InstCombine] clean up foldSelectOpOp(); NFCSanjay Patel2016-11-111-10/+4
| | | | llvm-svn: 286664
* [tsan][llvm] Implement the function attribute to disable TSan checking at ↵Anna Zaks2016-11-111-0/+23
| | | | | | | | | | | | | | | | | | | | | | | run time This implements a function annotation that disables TSan checking for the function at run time. The benefit over attribute((no_sanitize("thread"))) is that the accesses within the callees will also be suppressed. The motivation for this attribute is a guarantee given by the objective C language that the calls to the reference count decrement and object deallocation will be synchronized. To model this properly, we would need to intercept all ref count decrement calls (which are very common in ObjC due to use of ARC) and also every single message send. Instead, we propose to just ignore all accesses made from within dealloc at run time. The main downside is that this still does not introduce any synchronization, which means we might still report false positives if the code that relies on this synchronization is not executed from within dealloc. However, we have not seen this in practice so far and think these cases will be very rare. Differential Revision: https://reviews.llvm.org/D25858 llvm-svn: 286663
* [LV] Stop saying "use -Rpass-analysis=loop-vectorize"Adam Nemet2016-11-111-2/+1
| | | | | | | | | | | | | | | | | | This is PR28376. Unfortunately given the current structure of optimization diagnostics we lack the capability to tell whether the user has passed -Rpass-analysis=loop-vectorize since this is local to the front-end (BackendConsumer::OptimizationRemarkHandler). So rather than printing this even if the user has already passed -Rpass-analysis, this patch just punts and stops recommending this option. I don't think that getting this right is worth the complexity. Differential Revision: https://reviews.llvm.org/D26563 llvm-svn: 286662
* Revert "(origin/master, origin/HEAD) MachineScheduler/ScheduleDAG: Add ↵Matthias Braun2016-11-112-11/+0
| | | | | | | | | | support to skipping a node." Revert accidentally committed change. This reverts commit r286655. llvm-svn: 286656
* MachineScheduler/ScheduleDAG: Add support to skipping a node.Matthias Braun2016-11-112-0/+11
| | | | | | | | | | | The DAG mutators in the scheduler cannot really remove DAG nodes as additional anlysis information such as ScheduleDAGToplogicalSort are already computed at this point and rely on a fixed number of DAG nodes. Alleviate the missing removal with a new flag: Setting the new skip flag on a node ignores it during scheduling. llvm-svn: 286655
* ScheduleDAGInstrs: Move VRegUses to ScheduleDAGMILive; NFCIMatthias Braun2016-11-112-43/+43
| | | | | | | | | | | | | Push VRegUses/collectVRegUses() down the class hierarchy towards its only user ScheduleDAGMILive. NFCI: The initialization of the map happens at a later point but that should not matter. This is in preparation to allow DAG mutators to merge nodes, which relies on this map getting computed later. llvm-svn: 286654
* MachineScheduler: Dump EntrySU/ExitSU if possibleMatthias Braun2016-11-111-2/+12
| | | | llvm-svn: 286653
* ScheduleDAG: Identify EntrySU/ExitSU when dumping node idsMatthias Braun2016-11-111-3/+13
| | | | llvm-svn: 286652
* FunctionComparator: don't rely on argument evaluation order.Erik Eckstein2016-11-111-1/+3
| | | | | | | This is a follow-up on the recent refactoring of the FunctionMerge pass. It should fix a fail of the new FunctionComparator unittest whe compiling with MSVC. llvm-svn: 286648
* Simplify code and address review comments (NFC)Adrian Prantl2016-11-111-4/+3
| | | | llvm-svn: 286644
* Fix a reference-to-temporary introduced in r286607.Adrian Prantl2016-11-111-8/+10
| | | | llvm-svn: 286640
* [ORC] Re-apply 286620 with fixes for the ErrorSuccess class.Lang Hames2016-11-113-54/+2
| | | | llvm-svn: 286639
* [PowerPC] Add remaining vector permute builtins in altivec.h - LLVM portionNemanja Ivanovic2016-11-112-5/+23
| | | | | | | | | | This patch corresponds to review: https://reviews.llvm.org/D26480 Adds all the intrinsics used for various permute builtins that will be added to altivec.h. llvm-svn: 286638
* [cfi] Fix weak functions handling.Evgeniy Stepanov2016-11-111-2/+74
| | | | | | | | | | | | | | | When a function pointer is replaced with a jumptable pointer, special case is needed to preserve the semantics of extern_weak functions. Since a jumptable entry can not be extern_weak, we emulate that behaviour by replacing all references to F (the extern_weak function) with the following expression: F != nullptr ? JumpTablePtr : nullptr. Extra special care is needed for global initializers, since most (or probably all) backends can not lower an initializer that includes this kind of constant expression. Initializers like that are replaced with a global constructor (i.e. a runtime initializer). llvm-svn: 286636
* Make the FunctionComparator of the MergeFunctions pass a stand-alone utility.Erik Eckstein2016-11-113-1217/+924
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is pure refactoring. NFC. This change moves the FunctionComparator (together with the GlobalNumberState utility) in to a separate file so that it can be used by other passes. For example, the SwiftMergeFunctions pass in the Swift compiler: https://github.com/apple/swift/blob/master/lib/LLVMPasses/LLVMMergeFunctions.cpp Details of the change: *) The big part is just moving code out of MergeFunctions.cpp into FunctionComparator.h/cpp *) Make FunctionComparator member functions protected (instead of private) so that a derived comparator class can use them. Following refactoring helps to share code between the base FunctionComparator class and a derived class: *) Add a beginCompare() function *) Move some basic function property comparisons into a separate function compareSignature() *) Do the GEP comparison inside cmpOperations() which now has a new needToCmpOperands reference parameter https://reviews.llvm.org/D25385 llvm-svn: 286632
* Fix -Wpessimizing-move warning.Rui Ueyama2016-11-111-1/+1
| | | | llvm-svn: 286629
* Fixed the lost FastMathFlags for FCmp operations in SLPVectorizer.Vyacheslav Klochkov2016-11-111-3/+4
| | | | | | | Reviewer: Michael Zolotukhin. Differential Revision: https://reviews.llvm.org/D26543 llvm-svn: 286626
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