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* Don't treat a partial <def,undef> operand as a read.Jakob Stoklund Olesen2011-08-191-1/+2
| | | | | | | | | | | | | | | | | | | | | | | Normally, a partial register def is treated as reading the super-register unless it also defines the full register like this: %vreg110:sub_32bit<def> = COPY %vreg77:sub_32bit, %vreg110<imp-def> This patch also uses the <undef> flag on partial defs to recognize non-reading operands: %vreg110:sub_32bit<def,undef> = COPY %vreg77:sub_32bit This fixes a subtle bug in RegisterCoalescer where LIS->shrinkToUses would treat a coalesced copy as still reading the register, extending the live range artificially. My test case only works when I disable DCE so a dead copy is left for RegisterCoalescer, so I am not including it. <rdar://problem/9967101> llvm-svn: 138018
* Track a retain+release nesting level independently of theDan Gohman2011-08-191-36/+64
| | | | | | | | known-incremented level, because the two concepts can be used to prove the saftey of a retain+release removal in different ways. llvm-svn: 138016
* Intelligently split the landing pad block.Bill Wendling2011-08-191-5/+16
| | | | | | | | | | We have to be careful when splitting the landing pad block, because the landingpad instruction is required to remain as the first non-PHI of an invoke's unwind edge. To retain this, we split the block into two blocks, moving the predecessors within the loop to one block and the remaining predecessors to the other. The landingpad instruction is cloned into the new blocks. llvm-svn: 138015
* Add SplitLandingPadPredecessors().Bill Wendling2011-08-191-1/+95
| | | | | | | | | | | | | | | | SplitLandingPadPredecessors is similar to SplitBlockPredecessors in that it splits the current block and attaches a set of predecessors to the new basic block. However, it differs from SplitBlockPredecessors in that it's specifically designed to handle landing pad blocks. Two new basic blocks are created: one that is has the vector of predecessors as its predecessors and one that has the remaining predecessors as its predecessors. Those two new blocks then receive a cloned copy of the landingpad instruction from the original block. The landingpad instructions are joined in a PHI, etc. Like SplitBlockPredecessors, it updates the LLVM IR, AliasAnalysis, DominatorTree, DominanceFrontier, LoopInfo, and LCCSA analyses. llvm-svn: 138014
* Re-encoded 128-bit AVX versions of SQRT, RSQRT, RCP have 3 operandsBruno Cardoso Lopes2011-08-181-31/+64
| | | | | | | | | | | | | | | | | | instead of 2. They were already defined this way in their regular version, but not for the intrinsics versions (*_Int), and that would work for assembly emission but not for object code, since a MachineOperand would be missing. This commit fix PR10697. Also removed the {VSQRT,VRSQRT,VRCP}r_Int forms and match the intrinsic via INSERT_SUBREG+EXTRACT_SUBREG patterns. The same couldn't be done for memory versions because sse_load_f32/sse_load_f64 operand need special handling and don't work like regular "addr" operands. There are right now 114 "*_Int" and 98 "Int_*" forms! I'm slowly removing them as I step through, but hope we can get rid of these someday, they are really annoying :) llvm-svn: 138012
* There is no need to add file as context for subroutine type. The subroutine ↵Devang Patel2011-08-181-2/+2
| | | | | | type does not need any context. llvm-svn: 138010
* add the comments of each declaration follow it, making it easier to read and ↵Renato Golin2011-08-181-49/+44
| | | | | | compare to GCC's result. llvm-svn: 138009
* Use 'getFirstInsertionPt' when trying to insert new instructions during LICM.Bill Wendling2011-08-181-3/+3
| | | | llvm-svn: 138008
* Use subword loads instead of a 4-byte load when the size of a structure (or aAkira Hatanaka2011-08-181-26/+73
| | | | | | piece of it) that is being passed by value is smaller than a word. llvm-svn: 138007
* Eliminate unnecessary forwarding function.Devang Patel2011-08-183-19/+6
| | | | llvm-svn: 138006
* Add NativeClient operating system support.Ivan Krasin2011-08-181-0/+1
| | | | | | | | | | | | | | This patch adds support of NativeClient (*-*-nacl) OS support to LLVM. It's already supported in autoconf/config.sub. The motivation for this change is to start upstreaming PNaCl work. The whole set of patches include llvm backends (i686, x86_64, ARM), llvm-gcc (probably, would not be upstreamed because it's deprecated) and clang (the work has been just started, the amount of changes is going to be low and the most of the work is expected to be done close to the mainline). llvm-svn: 138005
* STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST ↵Owen Anderson2011-08-181-0/+4
| | | | | | | | for the purposes of decoding all operands except the predicate. Found by randomized testing. llvm-svn: 138003
* Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs ↵Owen Anderson2011-08-181-8/+42
| | | | | | have it unset. llvm-svn: 138000
* Add new DIE into the map asap.Devang Patel2011-08-181-8/+6
| | | | llvm-svn: 137998
* Remember to fill in some operands so we can print _something_ coherent even ↵Owen Anderson2011-08-181-1/+4
| | | | | | when decoding the CPS instruction soft-fails. llvm-svn: 137997
* Improve handling of failure and unpredictable cases for CPS, STR, and SMLA ↵Owen Anderson2011-08-181-11/+18
| | | | | | | | instructions. Fixes a large class of disassembler crashes found by randomized testing. llvm-svn: 137995
* FastISel: avoid function calls between the materialization of the constant ↵Ivan Krasin2011-08-181-5/+20
| | | | | | and its use. llvm-svn: 137993
* Thumb assembly parsing and encoding for LDM instruction.Jim Grosbach2011-08-183-5/+33
| | | | | | | | Fix base register type and canonicallize to the "ldm" spelling rather than "ldmia." Add diagnostics for incorrect writeback token and out-of-range registers. llvm-svn: 137986
* Make it clear that this code is iterating in reverse order through the array.Dan Gohman2011-08-181-2/+3
| | | | llvm-svn: 137985
* Revert r137871. The loop simplify pass should require all exits from a loop thatBill Wendling2011-08-181-15/+3
| | | | | | aren't from an indirect branch need to be dominated by the loop header. llvm-svn: 137981
* Split out the updating of PHI nodes after splitting the BB into a separateBill Wendling2011-08-181-43/+53
| | | | | | function. llvm-svn: 137979
* Use this fantzy ArrayRef thing to pass in the list of predecessors.Bill Wendling2011-08-181-9/+14
| | | | llvm-svn: 137978
* Make IsShiftedMask a static function rather than defining it in anAkira Hatanaka2011-08-181-16/+14
| | | | | | anonymous namespace. llvm-svn: 137975
* The edge from DISubprogram to DICompileUnit has been removed in recent versionsNick Lewycky2011-08-181-1/+1
| | | | | | of debug info. llvm-svn: 137972
* Thumb assembly parsing and encoding for CMP.Jim Grosbach2011-08-181-1/+1
| | | | llvm-svn: 137963
* Use static instead of anonymous namespace.Bill Wendling2011-08-181-7/+4
| | | | llvm-svn: 137959
* Thumb instructions CBZ and CBNZ are Thumb2, not THumb1.Jim Grosbach2011-08-182-25/+28
| | | | llvm-svn: 137956
* Rip out the old StructType APIs as warned about on llvmdev last week.Chris Lattner2011-08-181-38/+0
| | | | llvm-svn: 137953
* ARM Thumb blx instruction fixup has same data range as bl.Jim Grosbach2011-08-181-1/+1
| | | | | | | | | These fixups are handled poorly in general, and should have a single contiguous range of bits per fixup type, but that's not how they're currently organized, so for now in complex ones like for blx, we just tell the emitter it's OK for the fixup to munge any bit it wants. llvm-svn: 137947
* 80 columns.Jim Grosbach2011-08-181-1/+1
| | | | llvm-svn: 137946
* Clenup and fix encoding for Mips ins and ext instructionBruno Cardoso Lopes2011-08-181-17/+13
| | | | llvm-svn: 137943
* Add missing 'break'.Jim Grosbach2011-08-181-0/+1
| | | | llvm-svn: 137941
* Add intrinsics for SETEV, GETED, GETET.Richard Osborne2011-08-181-7/+21
| | | | llvm-svn: 137938
* Remove unused variable.Duncan Sands2011-08-181-1/+0
| | | | llvm-svn: 137933
* Split out the analysis updating code into a helper function. No intendedBill Wendling2011-08-181-63/+78
| | | | | | functionality change. llvm-svn: 137926
* Cleanup vector logical ops in AVX and add use int versions for simpleBruno Cardoso Lopes2011-08-181-20/+20
| | | | | | v2i64 llvm-svn: 137919
* Dramatically speedup codegen prepare by a) avoiding use of dominator tree ↵Devang Patel2011-08-181-16/+38
| | | | | | and b) doing a separate pass over dbg.value instructions. llvm-svn: 137908
* Remove extraneous newline from operand print method. PR10569.Jim Grosbach2011-08-171-3/+3
| | | | llvm-svn: 137900
* Clean up patterns for Thumb1 system instructions.Jim Grosbach2011-08-171-24/+18
| | | | llvm-svn: 137897
* Changed definition of EXT and INS per Bruno's comments.Akira Hatanaka2011-08-173-39/+29
| | | | llvm-svn: 137892
* Thumb assembly parsing and encoding for B.Jim Grosbach2011-08-171-0/+4
| | | | llvm-svn: 137891
* Do not use DebugInfoFinder. Extract debug info directly from llvm.dbg.cu ↵Devang Patel2011-08-171-159/+162
| | | | | | named mdnode. llvm-svn: 137890
* Thumb assembly parsing and encoding for ASR.Jim Grosbach2011-08-171-1/+1
| | | | llvm-svn: 137889
* Atomic load/store handling for the passes using memdep (GVN, DSE, memcpyopt).Eli Friedman2011-08-173-9/+11
| | | | llvm-svn: 137888
* Fix PR10688. Add support for spliting 256-bit vector shifts when theBruno Cardoso Lopes2011-08-171-11/+20
| | | | | | shift amount is variable llvm-svn: 137885
* Tidy up. 80 columns.Jim Grosbach2011-08-171-34/+49
| | | | llvm-svn: 137881
* Add the support in code-gen for the landingpad instruction lowering.Bill Wendling2011-08-172-3/+70
| | | | | | | | | | The landingpad instruction is lowered into the EXCEPTIONADDR and EHSELECTION SDNodes. The information from the landingpad instruction is harvested by the 'AddLandingPadInfo' function. The new EH uses the current EH scheme in the back-end. This will change once we switch over to the new scheme. (Reviewed by Jakob!) llvm-svn: 137880
* ARM clean up the imm_sr operand class representation.Jim Grosbach2011-08-178-29/+36
| | | | | | | | | Represent the operand value as it will be encoded in the instruction. This allows removing the specialized encoder and decoder methods entirely. Add an assembler match class while we're at it to lay groundwork for parsing the thumb shift instructions. llvm-svn: 137879
* Disable PRE for landing pads.Bill Wendling2011-08-171-2/+14
| | | | | | | | PRE needs the landing pads to have their critical edges split. Doing this for a landing pad is non-trivial. Abandon the attempt to perform PRE when we come across a landing pad. (Reviewed by Owen!) llvm-svn: 137876
* Revert patch. Forgot a dependent commit.Bill Wendling2011-08-171-39/+3
| | | | llvm-svn: 137875
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