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* [ARM] Make RWPI use movw/movt when availableChristof Douma2017-02-074-14/+45
| | | | | | | | | | | | | | | | | When constructing global address literals while targeting the RWPI relocation model. LLVM currently only uses literal pools. If MOVW/MOVT instructions are available we can use these instead. Beside being more efficient it allows -arm-execute-only to work with -relocation-model=RWPI as well. When we generate MOVW/MOVT for global addresses when targeting the RWPI relocation model, we need to use base relative relocations. This patch does the needed plumbing in MC to generate these for MOVW/MOVT. Differential Revision: https://reviews.llvm.org/D29487 Change-Id: I446786e43a6f5aa9b6a5bb2cd216d60d41c7755d llvm-svn: 294298
* [APInt] Fix rotl/rotr when the shift amount is greater than the total bit width.Joey Gouly2017-02-071-2/+15
| | | | | Review: https://reviews.llvm.org/D27749 llvm-svn: 294295
* Revert "[DAGCombiner] (add X, (adde Y, 0, Carry)) -> (adde X, Y, Carry)"Daniel Jasper2017-02-071-6/+0
| | | | | | | | | | | | | This reverts commit r294186. On an internal test, this triggers an out-of-memory error on PPC, presumably because there is another dagcombine that does the exact opposite triggering and endless loop consuming more and more memory. Chandler has started at creating a reduced test case and we'll attach it as soon as possible. llvm-svn: 294288
* [AVX-512] Add masked and unmasked shift by immediate instructions to load ↵Craig Topper2017-02-071-0/+81
| | | | | | folding tables. llvm-svn: 294287
* [AVX-512] Add masked shift instructions to load folding tables.Craig Topper2017-02-071-0/+108
| | | | | | This adds the masked versions of everything, but the shift by immediate instructions. llvm-svn: 294286
* [AVX-512] Add some of the shift instructions to the load folding tables.Craig Topper2017-02-071-0/+49
| | | | | | | | This includes unmasked forms of variable shift and shifting by the lower element of a register. Still need to do shift by immediate which was not foldable prior to avx512 and all the masked forms. llvm-svn: 294285
* AMDGPU: Fix missing staticMatt Arsenault2017-02-071-3/+4
| | | | llvm-svn: 294281
* [X86] Change the Defs list for VZEROALL/VZEROUPPER back to not including ↵Craig Topper2017-02-071-3/+2
| | | | | | YMM16-31. llvm-svn: 294277
* LowerTypeTests: Simplify. NFC.Peter Collingbourne2017-02-071-5/+3
| | | | llvm-svn: 294273
* [Hexagon] Address ASAN and UBSAN failures after r294226Krzysztof Parzyszek2017-02-074-16/+18
| | | | | | Reinstate r294256 with a fix. llvm-svn: 294269
* RegisterCoalescer: Fix joinReservedPhysReg()Matthias Braun2017-02-071-0/+5
| | | | | | | | | | | joinReservedPhysReg() can only deal with a liverange in a single basic block when copying from a vreg into a physreg. See also rdar://30306405 Differential Revision: https://reviews.llvm.org/D29436 llvm-svn: 294268
* Revert r293017 and fix the actual underlying issue.Chandler Carruth2017-02-072-2/+3
| | | | | | | | | | | | | | | | | | | | | The patch committed in r293017, as discussed on the list, doesn't really make sense but was causing an actual issue to go away. The issue turns out to be that in one place the extra template arguments were dropped from the OuterAnalysisManagerProxy. This in turn caused the types used in one set of places to access the key to be completely different from the types used in another set of places for both Loop and CGSCC cases where there are extra arguments. I have literally no idea how anything seemed to work with this bug in place. It blows my mind. But it did except for mingw64 in a DLL build. I've added a really handy static assert that helps ensure we don't break this in the future. It immediately diagnoses the issue with a compile failure and a very clear error message. Much better that staring at backtraces on a build bot. =] llvm-svn: 294267
* [AMDGPU] Lower null pointers in static variable initializerYaxun Liu2017-02-073-0/+39
| | | | | | | | | | | | For amdgcn target Clang generates addrspacecast to represent null pointers in private and local address spaces. In LLVM codegen, the static variable initializer is lowered by virtual function AsmPrinter::lowerConstant which is target generic. Since addrspacecast is target specific, AsmPrinter::lowerConst This patch overrides AsmPrinter::lowerConstant with AMDGPUAsmPrinter::lowerConstant, which is able to lower the target-specific addrspacecast in the null pointer representation so that -1 is co Differential Revision: https://reviews.llvm.org/D29284 llvm-svn: 294265
* [LVI] Switch from BFS to DFS exploration orderPhilip Reames2017-02-071-14/+16
| | | | | | | | | | | | | | This patch changes the order in which LVI explores previously unexplored paths. Previously, the code used an BFS strategy where each unexplored input was added to the search queue before any of them were explored. This has the effect of causing all inputs to be explored before returning to re-evaluate the merge point (non-local or phi node). This has the unfortunate property of doing redundant work if one of the inputs to the merge is found to be overdefined (i.e. unanalysable). If any input is overdefined, the result of the merge will be too; regardless of the values of other inputs. The new code uses a DFS strategy where we re-evaluate the merge after evaluating each input. If we discover an overdefined input, we immediately return without exploring other inputs. We have reports of large (4-10x) improvements of compile time with this patch and some reports of more precise analysis results as well. See the review discussion for details. The original motivating case was pr10584. Differential Revision: https://reviews.llvm.org/D28190 llvm-svn: 294264
* GlobalISel: legalize narrow G_SELECTS on AArch64.Tim Northover2017-02-062-1/+27
| | | | | | Otherwise there aren't any patterns to select them. llvm-svn: 294261
* Fix the samplepgo indirect call promotion bug: we should not promote a ↵Dehao Chen2017-02-061-1/+2
| | | | | | | | | | | | | | | | direct call. Summary: Checking CS.getCalledFunction() == nullptr does not necessary indicate indirect call. We also need to check if CS.getCalledValue() is not a constant. Reviewers: davidxl Reviewed By: davidxl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29570 llvm-svn: 294260
* Revert "[Hexagon] Address ASAN and UBSAN failures after r294226"Krzysztof Parzyszek2017-02-063-15/+13
| | | | | | | This reverts commit r294256. It seems to be causing more problems instead of solving them. llvm-svn: 294259
* [Hexagon] Adding gp+ to the syntax of gp-relative instructionsKrzysztof Parzyszek2017-02-062-9/+65
| | | | | | Patch by Colin LeMahieu. llvm-svn: 294258
* [AMDGPU] Fix GCNSchedStrategy.cpp debug outputStanislav Mekhanoshin2017-02-061-2/+2
| | | | | | | | There is typo in the debug output: top and bottom candidates are switched. Differential Revision: https://reviews.llvm.org/D29608 llvm-svn: 294257
* [Hexagon] Address ASAN and UBSAN failures after r294226Krzysztof Parzyszek2017-02-063-13/+15
| | | | llvm-svn: 294256
* Merge DebugLoc on combined stores; in this case, when combining storesPaul Robinson2017-02-061-1/+4
| | | | | | | | from the end of two blocks, merge instead of arbitrarily picking one. Differential Revision: http://reviews.llvm.org/D29504 llvm-svn: 294251
* [GVNHoist] Merge DebugLoc metadata on hoisted instructionsTaewook Oh2017-02-061-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When instructions are hoisted, current implementation keeps DebugLoc metadata of the instruction that chosen as Repl (and its GEP operand if Repl is a load or a store). However, DebugLoc metadata should be updated to the 'merged' location across all hoisted instructions. See the following example code: ``` 1: typedef struct { 2: int a[10]; 3: } S1; 4: 5: extern S1 *s1[10]; 6: 7: void foo(int x, int y, int i) { 8: if (y) 9: s1[i]->a[i] = x + y; 10: else 11: s1[i]->a[i] = x; 12: } ``` Below is LLVM IR representation of the program before gvn-hoist: ``` %struct.S1 = type { [10 x i32] } @s1 = external local_unnamed_addr global [10 x %struct.S1*], align 16 define void @foo(i32 %x, i32 %y, i32 %i) !dbg !4 { entry: %tobool = icmp ne i32 %y, 0, !dbg !8 br i1 %tobool, label %if.then, label %if.else, !dbg !10 if.then: ; preds = %entry %add = add nsw i32 %x, %y, !dbg !11 %idxprom = sext i32 %i to i64, !dbg !12 %arrayidx = getelementptr inbounds [10 x %struct.S1*], [10 x %struct.S1*]* @s1, i64 0, i64 %idxprom, !dbg !12 %0 = load %struct.S1*, %struct.S1** %arrayidx, align 8, !dbg !12, !tbaa !13 %a = getelementptr inbounds %struct.S1, %struct.S1* %0, i32 0, i32 0, !dbg !17 br label %if.end, !dbg !12 if.else: ; preds = %entry %idxprom3 = sext i32 %i to i64, !dbg !18 %arrayidx4 = getelementptr inbounds [10 x %struct.S1*], [10 x %struct.S1*]* @s1, i64 0, i64 %idxprom3, !dbg !18 %1 = load %struct.S1*, %struct.S1** %arrayidx4, align 8, !dbg !18, !tbaa !13 %a5 = getelementptr inbounds %struct.S1, %struct.S1* %1, i32 0, i32 0, !dbg !19 br label %if.end if.end: ; preds = %if.else, %if.then %a5.sink = phi [10 x i32]* [ %a5, %if.else ], [ %a, %if.then ] %.sink = phi i32 [ %x, %if.else ], [ %add, %if.then ] %idxprom6 = sext i32 %i to i64 %arrayidx7 = getelementptr inbounds [10 x i32], [10 x i32]* %a5.sink, i64 0, i64 %idxprom6 store i32 %.sink, i32* %arrayidx7, align 4, !tbaa !20 ret void, !dbg !22 } ``` where ``` !11 = !DILocation(line: 9, column: 18, scope: !9) !12 = !DILocation(line: 9, column: 5, scope: !9) !18 = !DILocation(line: 11, column: 5, scope: !9) !19 = !DILocation(line: 11, column: 9, scope: !9) ``` . And below is after gvn-hoist: ``` define void @foo(i32 %x, i32 %y, i32 %i) !dbg !4 { entry: %tobool = icmp ne i32 %y, 0, !dbg !8 %idxprom = sext i32 %i to i64, !dbg !10 %0 = getelementptr inbounds [10 x %struct.S1*], [10 x %struct.S1*]* @s1, i64 0, i64 %idxprom, !dbg !10 %1 = load %struct.S1*, %struct.S1** %0, align 8, !dbg !10, !tbaa !11 br i1 %tobool, label %if.then, label %if.else, !dbg !15 if.then: ; preds = %entry %add = add nsw i32 %x, %y, !dbg !16 %arrayidx = getelementptr inbounds [10 x %struct.S1*], [10 x %struct.S1*]* @s1, i64 0, i64 %idxprom, !dbg !10 %a = getelementptr inbounds %struct.S1, %struct.S1* %1, i32 0, i32 0, !dbg !17 br label %if.end, !dbg !10 if.else: ; preds = %entry %arrayidx4 = getelementptr inbounds [10 x %struct.S1*], [10 x %struct.S1*]* @s1, i64 0, i64 %idxprom, !dbg !18 %a5 = getelementptr inbounds %struct.S1, %struct.S1* %1, i32 0, i32 0, !dbg !19 br label %if.end if.end: ; preds = %if.else, %if.then %a5.sink = phi [10 x i32]* [ %a5, %if.else ], [ %a, %if.then ] %.sink = phi i32 [ %x, %if.else ], [ %add, %if.then ] %arrayidx7 = getelementptr inbounds [10 x i32], [10 x i32]* %a5.sink, i64 0, i64 %idxprom store i32 %.sink, i32* %arrayidx7, align 4, !tbaa !20 ret void, !dbg !22 } ``` As you see, loads and their GEPs have been hosited from if.then/if.else block to entry block. However, DebugLoc metadata of these new instructions are still same as the instructions in if.then block, as they are moved/cloned from if.then block. This may result incorrect stepping and imprecise sample profile result. Reviewers: majnemer, pcc, sebpop Reviewed By: sebpop Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29377 llvm-svn: 294250
* GlobalISel: fall back gracefully when we can't map an operand's size.Tim Northover2017-02-063-28/+40
| | | | | | | | AArch64 was asserting when it was asked to provide a register-bank of a size it couldn't deal with (in this case an s128 IMPLICIT_DEF). But we want a robust fallback path so this isn't allowed. llvm-svn: 294248
* GlobalISel: legalize G_INSERT instructionsTim Northover2017-02-063-0/+103
| | | | | | | We don't handle all cases yet (see arm64-fallback.ll for an example), but this is enough to cover most common C++ code so it's a good place to start. llvm-svn: 294247
* [X86] Fix some Include What You Use warnings; other minor fixes (NFC).Eugene Zelenko2017-02-065-19/+37
| | | | | | This is preparation to reduce MCExpr.h dependencies.(vlsj-clangbuild)[622] llvm-svn: 294246
* [SLP] Revert "Allow using of extra values in horizontal reductions."Michael Kuperstein2017-02-061-67/+12
| | | | | | | | This breaks when one of the extra values is also a scalar that participates in the same vectorization tree which we'll end up reducing. llvm-svn: 294245
* IR: Consider two DISubprograms to be odr-equal if they have the same ↵Peter Collingbourne2017-02-061-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | template parameters. In ValueMapper we create new operands for MDNodes and rely on MDNode::replaceWithUniqued to create a new MDNode with the specified operands. However this doesn't always actually happen correctly for DISubprograms because when we uniquify the new node, we only odr-compare it with existing nodes (MDNodeSubsetEqualImpl<DISubprogram>::isDeclarationOfODRMember). Although the TemplateParameters field can refer to a distinct DICompileUnit via DITemplateTypeParameter::type -> DICompositeType::scope -> DISubprogram::unit, it is not currently included in the odr comparison. As a result, we can end up getting our original DISubprogram back, which means we will have a cloned module referring to the DICompileUnit in the original module, which causes a verification error. The fix I implemented was to consider TemplateParameters to be one of the odr-equal properties. But I'm a little uncomfortable with this. In general it seems unsound to rely on distinct MDNodes never being reachable from nodes which we only check odr-equality of. My only long term suggestion would be to separate odr-uniquing from full uniquing. Differential Revision: https://reviews.llvm.org/D29240 llvm-svn: 294240
* [libFuzzer] make code less clever to avoid fallthrough in switch (and in ↵Kostya Serebryany2017-02-061-3/+3
| | | | | | turn avoid compiler warnings). NFC. Suggested by Christian Holler. llvm-svn: 294239
* [PM/LCG] Fix the no-asserts build after r294227. Sorry for the noise.Chandler Carruth2017-02-061-0/+2
| | | | llvm-svn: 294235
* Get function start line number from DWARF infoDavid Blaikie2017-02-063-12/+35
| | | | | | | | | | | | | | | DWARF info contains info about the line number at which a function starts (DW_AT_decl_line). This patch creates a function to look up the start line number for a function, and returns it in DILineInfo when looking up debug info for a particular address. Patch by Simon Que! Reviewed By: dblaikie Differential Revision: https://reviews.llvm.org/D27962 llvm-svn: 294231
* [PM/LCG] Remove the lazy RefSCC formation from the LazyCallGraph duringChandler Carruth2017-02-062-171/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | iteration. The lazy formation of RefSCCs isn't really the most important part of the laziness here -- that has to do with walking the functions themselves -- and isn't essential to maintain. Originally, there were incremental update algorithms that relied on updates happening predominantly near the most recent RefSCC formed, but those have been replaced with ones that have much tighter general case bounds at this point. We do still perform asserts that only scale well due to this incrementality, but those are easy to place behind EXPENSIVE_CHECKS. Removing this simplifies the entire analysis by having a single up-front step that builds all of the RefSCCs in a direct Tarjan walk. We can even easily replace this with other or better algorithms at will and with much less confusion now that there is no iterator-based incremental logic involved. This removes a lot of complexity from LCG. Another advantage of moving in this direction is that it simplifies testing the system substantially as we no longer have to worry about observing and mutating the graph half-way through the RefSCC formation. We still need a somewhat special iterator for RefSCCs because we want the iterator to remain stable in the face of graph updates. However, this now merely involves relative indexing to the current RefSCC's position in the sequence which isn't too hard. Differential Revision: https://reviews.llvm.org/D29381 llvm-svn: 294227
* [Hexagon] Update MCTargetDescKrzysztof Parzyszek2017-02-0622-704/+1072
| | | | | | | | | | Changes include: - Updates to the instruction descriptor flags. - Improvements to the packet shuffler and checker. - Updates to the handling of certain relocations. - Better handling of duplex instructions. llvm-svn: 294226
* [ValueTracking] emit a remark when we detect a conflicting assumption (PR31809)Sanjay Patel2017-02-063-18/+39
| | | | | | | | | | | | This is a follow-up to D29395 where we try to be good citizens and let the user know that we've probably gone off the rails. This should allow us to resolve: https://llvm.org/bugs/show_bug.cgi?id=31809 Differential Revision: https://reviews.llvm.org/D29404 llvm-svn: 294208
* Fix the bug of samplepgo indirect call promption when type casting of the ↵Dehao Chen2017-02-061-1/+3
| | | | | | | | | | | | | | | | return value is needed. Summary: When type casting of the return value is needed, promoteIndirectCall will return the type casting instruction instead of the direct call. This patch changed to return the direct call instruction instead. Reviewers: davidxl Reviewed By: davidxl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29569 llvm-svn: 294205
* [AArch64] Fix incorrect MachinePointerInfo in splitStoreSplatJohn Brawn2017-02-061-2/+3
| | | | | | | | | | | When splitting up one store into several in splitStoreSplat we have to make sure we get the MachinePointerInfo right, otherwise alias analysis thinks they all store to the same location. This can then cause invalid scheduling later on. Differential Revision: https://reviews.llvm.org/D29446 llvm-svn: 294203
* [DAGCombiner] Support bswap as a part of load combine patternsArtur Pilipenko2017-02-061-0/+3
| | | | | | | | Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D29397 llvm-svn: 294201
* [InstCombine] simplify dyn_cast + isa; NFCISanjay Patel2017-02-061-6/+4
| | | | llvm-svn: 294198
* RuntimeDyldELF/AArch64: Implement basic GOT supportEugene Leviant2017-02-064-73/+176
| | | | | | | | | This patch implements two GOT relocations: R_AARCH64_ADR_GOT_PAGE and R_AARCH64_LD64_GOT_LO12_NC Differential revision: https://reviews.llvm.org/D28571 llvm-svn: 294191
* Add ADDC to SelectionDAG::computeKnownBits and ComputeNumSignBits.Amaury Sechet2017-02-061-1/+3
| | | | | | | | | | | | Summary: As per title. Reviewers: bkramer, sunfish, lattner, RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29521 llvm-svn: 294188
* [DAGCombiner] Make DAGCombiner smarter about overflowAmaury Sechet2017-02-062-20/+30
| | | | | | | | | | | | Summary: Leverage it to transform addc into add. Reviewers: mkuper, spatel, RKSimon, zvi Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29524 llvm-svn: 294187
* [DAGCombiner] (add X, (adde Y, 0, Carry)) -> (adde X, Y, Carry)Amaury Sechet2017-02-061-0/+6
| | | | | | | | | | | | Summary: This is extracted from D29443 . Reviewers: mkuper, spatel, RKSimon, zvi, bkramer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29564 llvm-svn: 294186
* [X86][SSE] Combine shuffle nodes with multiple uses if all the users are ↵Simon Pilgrim2017-02-062-9/+34
| | | | | | | | | | | | | | being combined. Currently we only combine shuffle nodes if they have a single user to prevent us from causing code bloat by splitting the shuffles into several different combines. We don't take into account that in some cases we will already have combined all the users during recursively calling up the shuffle tree. This patch keeps a list of all the shuffle nodes that have been combined so far and permits combining of further shuffle nodes if all its users are in that list. Differential Revision: https://reviews.llvm.org/D29399 llvm-svn: 294183
* [mips] dla expansion without the at registerSimon Dardis2017-02-061-29/+75
| | | | | | | | | | | | | | | | | Previously only the superscalar scheduled expansion of the dla macro for MIPS64 was implemented. If assembler temporary register is not available and the optional source register is not the destination register, synthesize the address using the naive solution of adds and shifts. This partially resolves PR/30383. Thanks to Sean Bruno for reporting the issue! Reviewers: slthakur, seanbruno Differential Revision: https://reviews.llvm.org/D29328 llvm-svn: 294182
* [SCEV] limit recursion depth and operands number in getAddExprDaniil Fukalov2017-02-061-19/+39
| | | | | | | | | | | | | | | | | | | | | for a quite big function with source like %add = add nsw i32 %mul, %conv %mul1 = mul nsw i32 %add, %conv %add2 = add nsw i32 %mul1, %add %mul3 = mul nsw i32 %add2, %add ; repeat couple of thousands times that can be produced by loop unroll, getAddExpr() tries to recursively construct SCEV and runs almost infinite time. Added recursion depth restriction (with new parameter to set it) Reviewers: sanjoy Subscribers: hfinkel, llvm-commits, mzolotukhin Differential Revision: https://reviews.llvm.org/D28158 llvm-svn: 294181
* [AVR] Use 'print' instead of 'dump'Dylan McKay2017-02-061-1/+1
| | | | | | This should fix an undefined reference on the AVR buildbot. llvm-svn: 294175
* [X86][GlobalISel] Add limited ret lowering support to the IRTranslator.Igor Breger2017-02-062-14/+114
| | | | | | | | | | | | | | | | Summary: Support return lowering for i8/i16/i32/i64/float/double, vector type supported for 64bit platform only. Support argument lowering for float/double types. Reviewers: t.p.northover, zvi, ab, rovka Reviewed By: zvi Subscribers: dberris, kristof.beyls, delena, llvm-commits Differential Revision: https://reviews.llvm.org/D29261 llvm-svn: 294173
* [AVX-512] Add VPSLLDQ/VPSRLDQ to load folding tables.Craig Topper2017-02-061-0/+6
| | | | llvm-svn: 294170
* [AVX-512] Add VPABSB/D/Q/W to load folding tables.Craig Topper2017-02-061-0/+34
| | | | llvm-svn: 294169
* [AVX-512] Add VSHUFPS/PD to load folding tables.Craig Topper2017-02-061-0/+16
| | | | llvm-svn: 294168
* [AVX-512] Add VPMULLD/Q/W instructions to load folding tables.Craig Topper2017-02-061-0/+27
| | | | llvm-svn: 294164
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