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* [ARM64] MOVK with sf=0 and hw<1>=1 is unallocated. Shift amount for ADD/SUB ↵Bradley Smith2014-04-091-0/+6
| | | | | | instructions is unallocated if shift > 4. llvm-svn: 205859
* [ARM64] Register-offset loads and stores with the 'option' field equal to ↵Bradley Smith2014-04-091-14/+5
| | | | | | 00x or 10x are undefined. llvm-svn: 205858
* Revert "YAMLIO: Encode ambiguous hex strings explicitly"Filipe Cabecinhas2014-04-091-4/+1
| | | | | | | | This reverts commit r205839. It broke several tests in lld. llvm-svn: 205857
* SLPVectorizer: Only vectorize intrinsics whose operands are widened equallyArnold Schwaighofer2014-04-092-26/+10
| | | | | | | | | The vectorizer only knows how to vectorize intrinics by widening all operands by the same factor. Patch by Tyler Nowicki! llvm-svn: 205855
* AVX-512: insert element to mask vector; store i1 dataElena Demikhovsky2014-04-093-1/+77
| | | | | | | Implemented INSERT_VECTOR_ELT operation for v16i1 and v8i1 vectors; Implemented "store" for i1 type llvm-svn: 205850
* Re-commit: [mips] abs.[ds], and neg.[ds] should be allowed regardless of ↵Daniel Sanders2014-04-093-80/+7
| | | | | | | | | | | | | | | | | | | -enable-no-nans-fp-math Summary: They behave in accordance with the Has2008 and ABS2008 configuration bits of the processor which are used to select between the 1985 and 2008 versions of IEEE 754. In 1985 mode, these instructions are arithmetic (i.e. they raise invalid operation exceptions when given NaN), in 2008 mode they are non-arithmetic (i.e. they are copies). nmadd.[ds], and nmsub.[ds] are still subject to -enable-no-nans-fp-math because the ISA spec does not explicitly state that they obey Has2008 and ABS2008. Fixed the issue with the previous version of this patch (r205628). A pre-existing 'let Predicate =' statement was removing some predicates that were necessary for FP64 to behave correctly. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3274 llvm-svn: 205844
* YAMLIO: Encode ambiguous hex strings explicitlyDavid Majnemer2014-04-091-1/+4
| | | | | | | | | | YAMLIO would turn a BinaryRef into the string 0000000004000000. However, the leading zero causes parsers to interpret it as being an octal number instead of a hexadecimal one. Instead, escape such strings as needed. llvm-svn: 205839
* Delinearize: Extend informationin -analyze outputTobias Grosser2014-04-091-0/+4
| | | | llvm-svn: 205838
* R600/SI: Match not instruction.Matt Arsenault2014-04-092-1/+5
| | | | llvm-svn: 205837
* ARM64: scalarize v1i64 mul operationTim Northover2014-04-091-0/+2
| | | | | | This is the second part of fixing PR19367. llvm-svn: 205836
* ARM64: add pattern for <1 x i64> custom not node.Tim Northover2014-04-091-0/+1
| | | | | | This should fix PR19367. llvm-svn: 205835
* Object: add type names for ARM/COFF relocationsSaleem Abdulrasool2014-04-091-0/+21
| | | | | | | Add type name mappings for the ARM COFF relocations. This allows for objdump to provide a more useful description of relocations in disassembly inline form. llvm-svn: 205834
* ARM MC: 80 columnSaleem Abdulrasool2014-04-091-3/+5
| | | | llvm-svn: 205833
* ARM MC: sort source files in CMakeListsSaleem Abdulrasool2014-04-091-3/+3
| | | | llvm-svn: 205832
* [C++11] More 'nullptr' conversion or in some cases just using a boolean ↵Craig Topper2014-04-0932-402/+414
| | | | | | check instead of comparing to nullptr. llvm-svn: 205831
* [C++11] Make use of 'nullptr' in TableGen library.Craig Topper2014-04-093-282/+275
| | | | llvm-svn: 205830
* [C++11] Replace some comparisons with 'nullptr' with simple boolean checks ↵Craig Topper2014-04-0912-34/+32
| | | | | | to reduce verbosity. llvm-svn: 205829
* WinCOFF: Emit common symbols as specified in the COFF specDavid Majnemer2014-04-084-32/+41
| | | | | | | | | | | | | | | | | | Summary: Local common symbols were properly inserted into the .bss section. However, putting external common symbols in the .bss section would give them a strong definition. Instead, encode them as undefined, external symbols who's symbol value is equivalent to their size. Reviewers: Bigcheese, rafael, rnk CC: llvm-commits Differential Revision: http://reviews.llvm.org/D3324 llvm-svn: 205811
* Bug 19348: Check for legal ExtLoad operation before foldingMatt Arsenault2014-04-081-9/+12
| | | | | | | | (aext (zextload x)) -> (aext (truncate (*extload x))) Patch by Stanislav Mekhanoshin! llvm-svn: 205805
* divide by the result of the gcdSebastian Pop2014-04-081-1/+1
| | | | | | used to fail with 'Step should divide Start with no remainder.' llvm-svn: 205802
* handle special cases when findGCD returns 1Sebastian Pop2014-04-081-1/+6
| | | | | | used to fail with 'Step should divide Start with no remainder.' llvm-svn: 205801
* in findGCD of multiply expr return the gcdSebastian Pop2014-04-081-2/+4
| | | | | | we used to return 1 instead of the gcd llvm-svn: 205800
* [Constant Hoisting][ARM64] Enable constant hoisting for ARM64.Juergen Ributzka2014-04-081-13/+131
| | | | | | | | This implements the target-hooks for ARM64 to enable constant hoisting. This fixes <rdar://problem/14774662> and <rdar://problem/16381500>. llvm-svn: 205791
* RegAlloc: Account for a variable entry block frequencyDuncan P. N. Exon Smith2014-04-082-13/+58
| | | | | | | | | | | | | | | | | | | | Until r197284, the entry frequency was constant -- i.e., set to 2^14. Although current ToT still has a constant entry frequency, since r197284 that has been an implementation detail (which is soon going to change). - r204690 made the wrong assumption for the CSRCost metric. Adjust callee-saved register cost based on entry frequency. - r185393 made the wrong assumption (although it was valid at the time). Update SpillPlacement.cpp::Threshold to be relative to the entry frequency. Since ToT still has 2^14 entry frequency, this should have no observable functionality change. <rdar://problem/14292693> llvm-svn: 205789
* [PowerPC] Don't return false from PPC::isVSLDOIShuffleMaskHal Finkel2014-04-081-1/+1
| | | | | | | | | PPC::isVSLDOIShuffleMask should return -1, not false, when the shuffle predicate should be false. Noticed by inspection; no test case (yet). llvm-svn: 205787
* Fix the ARM VLD3 (single 3-element structure to all lanes)Kevin Enderby2014-04-081-1/+1
| | | | | | | | | | | | | | | size 16 double-spaced registers instruction printing. This: vld3.16 {d0[], d2[], d4[]}, [r4]! was being printed as: vld3.16 {d0[], d1[], d2[]}, [r4]! rdar://16531387 llvm-svn: 205779
* Verifier: Give the right message for bad atomic loadsDuncan P. N. Exon Smith2014-04-081-2/+2
| | | | | | | | Talk about load (not store) on an invalid atomic load. <rdar://problem/16287567> llvm-svn: 205777
* Add -pass-remarks flag to 'opt'.Diego Novillo2014-04-083-1/+61
| | | | | | | | | | | | | | | | | | | | | Summary: This adds support in 'opt' to filter pass remarks emitted by optimization passes. A new flag -pass-remarks specifies which passes should emit a diagnostic when LLVMContext::emitOptimizationRemark is invoked. This will allow the front end to simply pass along the regular expression from its own -Rpass flag when launching the backend. Depends on D3227. Reviewers: qcolombet CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D3291 llvm-svn: 205775
* Add support for optimization reports.Diego Novillo2014-04-083-1/+43
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch adds backend support for -Rpass=, which indicates the name of the optimization pass that should emit remarks stating when it made a transformation to the code. Pass names are taken from their DEBUG_NAME definitions. When emitting an optimization report diagnostic, the lack of debug information causes the diagnostic to use "<unknown>:0:0" as the location string. This is the back end counterpart for http://llvm-reviews.chandlerc.com/D3226 Reviewers: qcolombet CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D3227 llvm-svn: 205774
* X86MCAsmInfoGNUCOFF: Set PointerSize as 8 for targeting x64. It caused ↵NAKAMURA Takumi2014-04-081-1/+3
| | | | | | | DW_LNE_set_address was misemitted on x64. FIXME: I haven't investigate whether CalleeSaveStackSlotSize should be 8. llvm-svn: 205772
* ARM64: fix fmsub patterns which assumed accum operand was firstTim Northover2014-04-081-4/+7
| | | | | | | | | | Confusingly, the NEON fmla instructions put the accumulator first but the scalar versions put it at the end (like the fma lib function & LLVM's intrinsic). This should fix PR19345, assuming there's only one issue. llvm-svn: 205758
* AVX-512: Added fp_to_uint and uint_to_fp patterns.Elena Demikhovsky2014-04-082-0/+13
| | | | llvm-svn: 205754
* Fix a (legacy) PassManager crash that occurs when a ModulePassAndrew Trick2014-04-081-6/+18
| | | | | | | | | indirectly requires a function analysis. This bug was reported by Jason Kim. He included a test case here: http://reviews.llvm.org/D3312 llvm-svn: 205753
* X86: Split the relocation selection upDavid Majnemer2014-04-081-29/+43
| | | | | | | | | | | Before, we would have conditional operators where one side of the operator would be of type RelocationTypeAMD64 and the other is of type RelocationTypeI386. GCC would noisly warn with -Wenum-compare diagnostic. Instead, refactor the code so it is more like the X86 ELF object writer. llvm-svn: 205752
* Tidy up comments a bit.Jim Grosbach2014-04-071-41/+41
| | | | | | Punctuation, grammar, formatting, etc.. llvm-svn: 205749
* ARM64: Range based for loop in ARM64PromoteConstant passJim Grosbach2014-04-071-9/+7
| | | | llvm-svn: 205748
* ARM64: Clean up file header comment a bit.Jim Grosbach2014-04-071-11/+9
| | | | llvm-svn: 205747
* obj2yaml: Use the correct relocation type for different machine typesDavid Majnemer2014-04-071-8/+24
| | | | | | | | | | | | | The IO normalizer would essentially lump I386 and AMD64 relocations together. Relocation types with the same numeric value would then get mapped in appropriately. For example: IMAGE_REL_AMD64_ADDR64 and IMAGE_REL_I386_DIR16 both have a numeric value of one. We would see IMAGE_REL_I386_DIR16 in obj2yaml conversions of object files with a machine type of IMAGE_FILE_MACHINE_AMD64. llvm-svn: 205746
* Reverting commit r205628 due to mips64 issues.Reed Kotler2014-04-073-2/+73
| | | | llvm-svn: 205741
* Put a limit on ScheduleDAGSDNodes::ClusterNeighboringLoads to avoid blowing ↵Andrew Trick2014-04-071-1/+6
| | | | | | | | | | | | | | | | | | | | up compile time. Fixes PR16365 - Extremely slow compilation in -O1 and -O2. The SD scheduler has a quadratic implementation of load clustering which absolutely blows up compile time for large blocks with constant pool loads. The MI scheduler has a better implementation of load clustering. However, we have not done the work yet to completely eliminate the SD scheduler. Some benchmarks still seem to benefit from early load clustering, although maybe by chance. As an intermediate term fix, I just put a nice limit on the number of DAG users to search before finding a match. With this limit there are no binary differences in the LLVM test suite, and the PR16365 test case does not suffer any compile time impact from this routine. llvm-svn: 205738
* R600/SI: Handle INSERT_SUBREG in SIFixSGPRCopiesTom Stellard2014-04-072-0/+12
| | | | llvm-svn: 205732
* R600: Match 24-bit arithmetic patterns in a Target DAGCombineTom Stellard2014-04-0711-58/+115
| | | | | | | | | | | | | | | | | Moving these patterns from TableGen files to PerformDAGCombine() should allow us to generate better code by eliminating unnecessary shifts and extensions earlier. This also fixes a bug where the MAD pattern was calling SimplifyDemandedBits with a 24-bit mask on the first operand even when the full pattern wasn't being matched. This occasionally resulted in some instructions being incorrectly deleted from the program. v2: - Fix bug with 64-bit mul llvm-svn: 205731
* R600: Replace dyn_cast + assert with castTom Stellard2014-04-071-2/+1
| | | | llvm-svn: 205730
* Use std::swapMatt Arsenault2014-04-071-3/+1
| | | | llvm-svn: 205723
* Use .data() instead of &x[0]Matt Arsenault2014-04-072-18/+21
| | | | llvm-svn: 205722
* Invert the option to enable debug info verification. No functionalEric Christopher2014-04-071-8/+7
| | | | | | change outside of the command line to enable it. llvm-svn: 205713
* Handle vlas during inline cost computation if they'll be turnedEric Christopher2014-04-071-1/+10
| | | | | | | | | | | into a constant size alloca by inlining. Ran a run over the testsuite, no results out of the noise, fixes the testcase in the PR. PR19115. llvm-svn: 205710
* Add NDEBUG markers around debug only function.Eric Christopher2014-04-071-0/+4
| | | | llvm-svn: 205706
* Add debug location information to the vectorizer debug statements.Eric Christopher2014-04-071-5/+29
| | | | | | Patch by Zinovy Nis. llvm-svn: 205705
* [C++11] Make use of 'nullptr' in the Support library.Craig Topper2014-04-0736-182/+184
| | | | llvm-svn: 205697
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