summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* [RS4GC] Clean up `find_index`; NFCSanjoy Das2015-10-201-11/+11
| | | | | | | - Bring it up to the LLVM Coding Style - Sink it inside `CreateGCRelocates`, which is its only user llvm-svn: 250785
* [RS4GC] Re-purpose `normalizeForInvokeSafepoint`; NFC.Sanjoy Das2015-10-201-9/+9
| | | | | | | | | | | | `normalizeForInvokeSafepoint` in RewriteStatepointsForGC.cpp, as it is written today, deals with `gc.relocate` and `gc.result` uses of a statepoint equally well. This change documents this fact and adds a test case. There is no functional change here -- only documentation of existing functionality. llvm-svn: 250784
* [RS4GC] Minor cleanup to `normalizeForInvokeSafepoint`; NFCSanjoy Das2015-10-201-3/+3
| | | | llvm-svn: 250783
* Sparc: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-202-5/+4
| | | | llvm-svn: 250781
* NVPTX: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-207-25/+20
| | | | llvm-svn: 250779
* Hexagon: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-2016-38/+34
| | | | | | | | | | | | | | | | | | | There are two things out of the ordinary in this commit. First, I made a loop obviously "infinite" in HexagonInstrInfo.cpp. After checking if an instruction was at the beginning of a basic block (in which case, `break`), the loop decremented and checked the iterator for `nullptr` as the loop condition. This has never been possible (the prev pointers are always been circular, so even with the weird ilist/iplist implementation, this isn't been possible), so I removed the condition. Second, in HexagonAsmPrinter.cpp there was another case of comparing a `MachineBasicBlock::instr_iterator` against `MachineBasicBlock::end()` (which returns `MachineBasicBlock::iterator`). While not incorrect, it's fragile. I switched this to `::instr_end()`. All that said, no functionality change intended here. llvm-svn: 250778
* WebAssembly: fix syntax for br_if.JF Bastien2015-10-203-5/+5
| | | | llvm-svn: 250777
* AsmPrinter: Remove implicit ilist iterator conversion, NFCDuncan P. N. Exon Smith2015-10-201-3/+3
| | | | llvm-svn: 250776
* Mips: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-209-40/+29
| | | | llvm-svn: 250769
* CppBackend: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-201-37/+26
| | | | | | | Mostly just converted to range-based for loops. May have converted a couple of extra loops as a drive-by (not sure). llvm-svn: 250766
* BPF: Remove implicit ilist iterator conversion, NFCDuncan P. N. Exon Smith2015-10-201-2/+1
| | | | llvm-svn: 250765
* ARM: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-199-45/+40
| | | | llvm-svn: 250759
* ObjCARC: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-195-53/+48
| | | | llvm-svn: 250756
* Enhance loop rotation with existence of profile data in ↵Cong Hou2015-10-191-3/+184
| | | | | | | | | | | | | | | | MachineBlockPlacement pass. Currently, in MachineBlockPlacement pass the loop is rotated to let the best exit to be the last BB in the loop chain, to maximize the fall-through from the loop to outside. With profile data, we can determine the cost in terms of missed fall through opportunities when rotating a loop chain and select the best rotation. Basically, there are three kinds of cost to consider for each rotation: 1. The possibly missed fall through edge (if it exists) from BB out of the loop to the loop header. 2. The possibly missed fall through edges (if they exist) from the loop exits to BB out of the loop. 3. The missed fall through edge (if it exists) from the last BB to the first BB in the loop chain. Therefore, the cost for a given rotation is the sum of costs listed above. We select the best rotation with the smallest cost. This is only for PGO mode when we have more precise edge frequencies. Differential revision: http://reviews.llvm.org/D10717 llvm-svn: 250754
* Linker: Remove implicit ilist iterator conversion, NFCDuncan P. N. Exon Smith2015-10-191-1/+1
| | | | llvm-svn: 250748
* Fix -Wdeprecated regarding ORC copying ValueMaterializersDavid Blaikie2015-10-191-1/+1
| | | | | | | | | | | | As usual, this is a polymorphic hierarchy without polymorphic ownership, so simply make the dtor protected non-virtual, protected default copy ctor/assign, and make derived classes final. The derived classes will pick up correct default public copy ops (and dtor) implicitly. (wish I could add -Wdeprecated to the build, but last time I tried it triggered on some system headers I still need to look into/figure out) llvm-svn: 250747
* [InstCombine] Optimize icmp of inc/dec at RHSMichael Liao2015-10-191-0/+20
| | | | | | | | | | | | | | | | Allow LLVM to optimize the sequence like the following: %inc = add nsw i32 %i, 1 %cmp = icmp slt %n, %inc into: %cmp = icmp sle i32 %n, %i The case is not handled previously due to the complexity of compuation of %n. Hence, LLVM cannot swap operands of icmp accordingly. llvm-svn: 250746
* Vectorize: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-193-85/+91
| | | | | | | | | | | | | Besides the usual, I finally added an overload to `BasicBlock::splitBasicBlock()` that accepts an `Instruction*` instead of `BasicBlock::iterator`. Someone can go back and remove this overload later (after updating the callers I'm going to skip going forward), but the most common call seems to be `BB->splitBasicBlock(BB->getTerminator(), ...)` and I'm not sure it's better to add `->getIterator()` to every one than have the overload. It's pretty hard to get the usage wrong. llvm-svn: 250745
* [CGP] transform select instructions into branches and sink expensive operandsSanjay Patel2015-10-191-16/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | This was originally checked in at r250527, but reverted at r250570 because of PR25222. There were at least 2 problems: 1. The cost check was checking for an instruction with an exact cost of TCC_Expensive; that should have been >=. 2. The cause of the clang stage 1 failures was illegally sinking 'call' instructions; we can't sink instructions that may have side effects / are not safe to execute speculatively. Fixed those conditions in sinkSelectOperand() and added test cases. Original commit message: This is a follow-up to the discussion in D12882. Ideally, we would like SimplifyCFG to be able to form select instructions even when the operands are expensive (as defined by the TTI cost model) because that may expose further optimizations. However, we would then like a later pass like CodeGenPrepare to undo that transformation if the target would likely benefit from not speculatively executing an expensive op (this patch). Once we have this safety mechanism in place, we can adjust SimplifyCFG to restore its select-formation behavior that changed with r248439. Differential Revision: http://reviews.llvm.org/D13297 llvm-svn: 250743
* X86: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-198-31/+24
| | | | llvm-svn: 250741
* [RuntimeDyld][COFF] Fix some endianness issues, re-enable the regression test.Lang Hames2015-10-191-10/+7
| | | | llvm-svn: 250733
* Restore the original behavior of SelectionDAG::getTargetIndex().Owen Anderson2015-10-191-1/+1
| | | | | | It looks like an extra negation snuck in as apart of restoring it. llvm-svn: 250726
* [Hexagon] Remove unnecessary argument sign extendsKrzysztof Parzyszek2015-10-193-0/+155
| | | | llvm-svn: 250724
* Pass FunctionInfoIndex by reference to WriteFunctionSummaryToFile (NFC)Teresa Johnson2015-10-191-8/+8
| | | | | | Implemented suggestion by dblakie in review for r250704. llvm-svn: 250723
* Add missing override noticed by Clang's -Winconsistent-missing-override.Benjamin Kramer2015-10-191-1/+1
| | | | llvm-svn: 250720
* [AArch64]Merge halfword loads into a 32-bit loadJun Bum Lim2015-10-191-45/+215
| | | | | | | | | | | | | Convert two halfword loads into a single 32-bit word load with bitfield extract instructions. For example : ldrh w0, [x2] ldrh w1, [x2, #2] becomes ldr w0, [x2] ubfx w1, w0, #16, #16 and w0, w0, #ffff llvm-svn: 250719
* [Hexagon] Fix debug information for local objectsKrzysztof Parzyszek2015-10-194-117/+170
| | | | | | | | | | | | - Isolate the check for the existence of a stack frame into hasFP. - Implement getFrameIndexReference for DWARF address computation. - Use getFrameIndexReference for offset computation in eliminateFrameIndex. - Preserve debug information for dynamically allocated stack objects. - Prefer FP to access local objects at -O0. - Add experimental code to skip allocframe when not strictly necessary (disabled by default). llvm-svn: 250718
* Put back SelectionDAG::getTargetIndex.Benjamin Kramer2015-10-191-0/+18
| | | | | | | While technically this is untested dead code, it has out-of-tree users. This reverts a part of r250434. llvm-svn: 250717
* [Hexagon] Delay emission of CFI instructionsKrzysztof Parzyszek2015-10-193-98/+178
| | | | | | | Emit the CFI instructions after all code transformation have been done. This will avoid any interference between CFI instructions and packetization. llvm-svn: 250714
* Revert "RegisterPressure: allocatable physreg uses are always kills"Matthias Braun2015-10-191-27/+25
| | | | | | | | | This reverts commit r250596. Reverted for now as the commit triggers assert in the AMDGPU target pending investigation. llvm-svn: 250713
* [Orc] Add support for emitting indirect stubs directly into the JIT target'sLang Hames2015-10-192-6/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | memory, rather than representing the stubs in IR. Update the CompileOnDemand layer to use this functionality. Directly emitting stubs is much cheaper than building them in IR and codegen'ing them (see below). It also plays well with remote JITing - stubs can be emitted directly in the target process, rather than having to send them over the wire. The downsides are: (1) Care must be taken when resolving symbols, as stub symbols are held in a separate symbol table. This is only a problem for layer writers and other people using this API directly. The CompileOnDemand layer hides this detail. (2) Aliases of function stubs can't be symbolic any more (since there's no symbol definition in IR), but must be converted into a constant pointer expression. This means that modules containing aliases of stubs cannot be cached. In practice this is unlikely to be a problem: There's no benefit to caching such a module anyway. On balance I think the extra performance is more than worth the trade-offs: In a simple stress test with 10000 dummy functions requiring stubs and a single executed "hello world" main function, directly emitting stubs reduced user time for JITing / executing by over 90% (1.5s for IR stubs vs 0.1s for direct emission). llvm-svn: 250712
* Remove CRLF newlines. NFC.Benjamin Kramer2015-10-191-6/+6
| | | | llvm-svn: 250698
* Fix mapping of @llvm.arm.ssat/usat intrinsics to ssat/usat instructionsAsiri Rathnayake2015-10-191-4/+4
| | | | | | | | | | | | | The mapping of these two intrinsics in ARMInstrInfo.td had a small omission which lead to their operands not being validated/transformed before being lowered into usat and ssat instructions. This can cause incorrect instructions to be emitted. I've also added tests for the remaining two saturating arithmatic intrinsics @llvm.arm.qadd and @llvm.arm.qsub as they are missing codegen tests. llvm-svn: 250697
* [GlobalsAA] Fix a really horrible iterator invalidation bugJames Molloy2015-10-191-1/+4
| | | | | | | | | | We were keeping a reference to an object in a DenseMap then mutating it. At the end of the function we were attempting to clone that reference into other keys in the DenseMap, but DenseMap may well decide to resize its hashtable which would invalidate the reference! It took an extremely complex testcase to catch this - many thanks to Zhendong Su for catching it in PR25225. This fixes PR25225. llvm-svn: 250692
* Removed parameter "Consecutive" from isLegalMaskedLoad() / isLegalMaskedStore().Elena Demikhovsky2015-10-195-24/+19
| | | | | | | | | | Originally I planned to use the same interface for masked gather/scatter and set isConsecutive to "false" in this case. Now I'm implementing masked gather/scatter and see that the interface is inconvenient. I want to add interfaces isLegalMaskedGather() / isLegalMaskedScatter() instead of using the "Consecutive" parameter in the existing interfaces. Differential Revision: http://reviews.llvm.org/D13850 llvm-svn: 250686
* [mips][microMIPS] Implement ADDQ.PH, ADDQ_S.W, ADDQH.PH, ADDQH.W, ADDSC, ↵Zlatko Buljan2015-10-193-21/+62
| | | | | | | | ADDU.PH, ADDU_S.QB, ADDWC and ADDUH.QB instructions Differential Revision: http://reviews.llvm.org/D13130 llvm-svn: 250685
* [mips][microMIPS] Implement ABSQ.QB, ABSQ_S.PH, ABSQ_S.W, ABSQ_S.QB, INSV, ↵Zlatko Buljan2015-10-193-10/+76
| | | | | | | | MADD, MADDU, MSUB, MSUBU, MULT and MULTU instructions Differential Revision: http://reviews.llvm.org/D13721 llvm-svn: 250683
* [PGO] Eliminate prof data register calls on FreeBSD platformXinliang David Li2015-10-191-1/+3
| | | | | | | This is a follow up patch of r250199 after verifying the start/stop section symbols work as spected on FreeBSD. llvm-svn: 250679
* Preserve CFG in MergedLoadStoreMotion. This fixes PR24426.Jakub Staszak2015-10-181-0/+1
| | | | llvm-svn: 250660
* Use SDValue bool check. NFCI.Simon Pilgrim2015-10-181-2/+2
| | | | llvm-svn: 250653
* Move one-use variable inside test. NFC.Simon Pilgrim2015-10-181-2/+1
| | | | llvm-svn: 250651
* [X86][AVX512DQ] add scalar fpclassAsaf Badouh2015-10-184-6/+61
| | | | | | Differential Revision: http://reviews.llvm.org/D13769 llvm-svn: 250650
* AVX512: Lowering i8/i16 vector CTLZ using the dword LZCNT vector instructionIgor Breger2015-10-182-23/+123
| | | | | | Differential Revision: http://reviews.llvm.org/D13632 llvm-svn: 250649
* [Sparc] Use MCPhysReg instead of unsigned to size static arrays of ↵Craig Topper2015-10-181-6/+7
| | | | | | registers. Should reduce the table size. llvm-svn: 250644
* Use array_lengthof. NFCCraig Topper2015-10-181-1/+1
| | | | llvm-svn: 250643
* Make a bunch of static arrays const.Craig Topper2015-10-1815-41/+48
| | | | llvm-svn: 250642
* [RuntimeDyld] Add support for absolute symbols.Lang Hames2015-10-183-18/+42
| | | | llvm-svn: 250639
* Minor Instr PGO code restructuringXinliang David Li2015-10-183-115/+42
| | | | | | | | | | | | | | | | 1. Key constant values (version, magic) and data structures related to raw and indexed profile format are moved into one centralized file: InstrProf.h. 2. Utility function such as MD5Hash computation is also moved to the common header to allow sharing with other components in the future. 3. A header data structure is introduced for Indexed format so that the reader and writer can always be in sync. 4. Added some comments to document different places where multiple definition of the data structure must be kept in sync (reader/writer, runtime, lowering etc). No functional change is intended. Differential Revision: http://reviews.llvm.org/D13758 llvm-svn: 250638
* [SCEV] Fix whitespace issues and remove extra braces; NFCSanjoy Das2015-10-181-10/+7
| | | | llvm-svn: 250636
* [SCEV] Use std::all_of and std::any_of; NFCSanjoy Das2015-10-181-16/+11
| | | | llvm-svn: 250635
OpenPOWER on IntegriCloud