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| author | Asiri Rathnayake <asiri.rathnayake@arm.com> | 2015-10-19 11:44:24 +0000 |
|---|---|---|
| committer | Asiri Rathnayake <asiri.rathnayake@arm.com> | 2015-10-19 11:44:24 +0000 |
| commit | 1040a53be3233c253da56210862eaea7ab06dee8 (patch) | |
| tree | 107f6b9db7a1ad498afa7329251c0b5930d646e5 /llvm/lib | |
| parent | b997792cc6ed531966e59515a389c98d176a93e2 (diff) | |
| download | bcm5719-llvm-1040a53be3233c253da56210862eaea7ab06dee8.tar.gz bcm5719-llvm-1040a53be3233c253da56210862eaea7ab06dee8.zip | |
Fix mapping of @llvm.arm.ssat/usat intrinsics to ssat/usat instructions
The mapping of these two intrinsics in ARMInstrInfo.td had a small
omission which lead to their operands not being validated/transformed
before being lowered into usat and ssat instructions. This can cause
incorrect instructions to be emitted.
I've also added tests for the remaining two saturating arithmatic
intrinsics @llvm.arm.qadd and @llvm.arm.qsub as they are missing
codegen tests.
llvm-svn: 250697
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrInfo.td | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td index 93ade1343d9..9506e1ebef7 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.td +++ b/llvm/lib/Target/ARM/ARMInstrInfo.td @@ -3678,10 +3678,10 @@ def USAT16 : AI<(outs GPRnopc:$Rd), let Inst{3-0} = Rn; } -def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos), - (SSAT imm:$pos, GPRnopc:$a, 0)>; -def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos), - (USAT imm:$pos, GPRnopc:$a, 0)>; +def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm1_32:$pos), + (SSAT imm1_32:$pos, GPRnopc:$a, 0)>; +def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm0_31:$pos), + (USAT imm0_31:$pos, GPRnopc:$a, 0)>; //===----------------------------------------------------------------------===// // Bitwise Instructions. |
