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* [mips] Remove asm string parameter from pseudo instructions. Add InstrItinClass Akira Hatanaka2012-12-206-69/+64
| | | | | | parameter. llvm-svn: 170661
* [mips] Delete definition of CPRESTORE instruction.Akira Hatanaka2012-12-201-8/+0
| | | | llvm-svn: 170660
* [mips] Refactor conditional branch instructions with one register operand.Akira Hatanaka2012-12-203-14/+24
| | | | | | Separate encoding information from the rest. llvm-svn: 170659
* Don't use isa<CallInst>(this) in the constructor for CallInst's base class.Richard Smith2012-12-201-2/+5
| | | | | | | | This has undefined behavior, because the classof implementation attempts to access parts of the not-yet-constructed derived class. Found by clang -fsanitize=vptr. llvm-svn: 170658
* [mips] Refactor conditional branch instructions with two register operands.Akira Hatanaka2012-12-203-8/+22
| | | | | | Separate encoding information from the rest. llvm-svn: 170657
* fix most of remaining issues with large frames.Reed Kotler2012-12-204-18/+195
| | | | | | | | | | these patches are tested a lot by test-suite but make check tests are forthcoming once the next few patches that complete this are committed. with the next few patches the pass rate for mips16 is near 100% llvm-svn: 170656
* [mips] Use "or $r0, $r1, $zero" instead of "addu $r0, $zero, $r1" to copyAkira Hatanaka2012-12-201-5/+5
| | | | | | | | | | | physical register $r1 to $r0. GNU disassembler recognizes an "or" instruction as a "move", and this change makes the disassembled code easier to read. Original patch by Reed Kotler. llvm-svn: 170655
* Fix use-before-construction of X86TargetLowering.Richard Smith2012-12-202-4/+4
| | | | llvm-svn: 170654
* Don't use -1 as a value of an unsigned 7-bit enumeration; that has undefinedRichard Smith2012-12-201-2/+1
| | | | | | | behavior and violates the !range constraints we put on loads of this enum. Found by clang -fsanitize=enum. llvm-svn: 170653
* [mips] Change the order of template parameters. Move the default parameters toAkira Hatanaka2012-12-202-29/+30
| | | | | | the end. llvm-svn: 170651
* [mips] Refactor shift instructions with register operands. Separate encodingAkira Hatanaka2012-12-203-15/+28
| | | | | | information from the rest. llvm-svn: 170650
* [mips] Refactor shift immediate instructions. Separate encoding informationAkira Hatanaka2012-12-203-36/+44
| | | | | | from the rest. llvm-svn: 170649
* [mips] Refactor arithmetic and logic instructions with immediate operands.Akira Hatanaka2012-12-203-22/+39
| | | | | | Separate encoding information from the rest. llvm-svn: 170648
* [mips] Refactor arithmetic and logic instructions. Separate encodingAkira Hatanaka2012-12-203-28/+40
| | | | | | information from the rest. llvm-svn: 170647
* [mips] Delete ArithOverflowR and ArithOverflow and use ArithLogicR andAkira Hatanaka2012-12-202-43/+30
| | | | | | ArithLogicI as the instruction base classes. llvm-svn: 170642
* Loop Vectorizer: Enable if-conversion.Nadav Rotem2012-12-201-1/+1
| | | | llvm-svn: 170632
* s/AttributesImpl/AttributeImpl/g This is going to apply to Attribute, not ↵Bill Wendling2012-12-204-22/+22
| | | | | | Attributes. llvm-svn: 170631
* Do not introduce vector operations in functions marked with noimplicitfloat.Bob Wilson2012-12-201-2/+5
| | | | | | <rdar://problem/12879313> llvm-svn: 170630
* whitespaceNadav Rotem2012-12-201-1/+1
| | | | llvm-svn: 170626
* Target/R600: Update MIB according to r170588.NAKAMURA Takumi2012-12-203-22/+29
| | | | llvm-svn: 170620
* Add a context so that once we uniquify strings we can access them easily.Bill Wendling2012-12-192-3/+6
| | | | llvm-svn: 170615
* MC: Add MCInstrDesc::mayAffectControlFlow() method.Jim Grosbach2012-12-194-6/+9
| | | | | | | | | MC disassembler clients (LLDB) are interested in querying if an instruction may affect control flow other than by virtue of being an explicit branch instruction. For example, instructions which write directly to the PC on some architectures. llvm-svn: 170610
* Refactor isIntrinsic() to be quicker, and change classof() (and thus, ↵Michael Ilseman2012-12-191-5/+1
| | | | | | isa<IntrinsicInst>()) to use it. This decreases the number of occurrences of the slow-path string matching performed by getIntrinsicID(). llvm-svn: 170602
* s/AttributeListImpl/AttributeSetImpl/g to match the namechange of AttributeList.Bill Wendling2012-12-194-12/+12
| | | | llvm-svn: 170600
* Add a missing 'else'. Found by grep '} if'Dmitri Gribenko2012-12-191-1/+1
| | | | | | No testcase because it is apparently not so trivial to construct. llvm-svn: 170595
* R600: Remove unecessary VREG alignment.Tom Stellard2012-12-191-6/+6
| | | | | | | | | | | Unlike SGPRs VGPRs doesn't need to be aligned. Patch by: Christian König Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Christian König <deathsimple@vodafone.de> llvm-svn: 170593
* R600: control flow optimizationTom Stellard2012-12-191-0/+49
| | | | | | | | | | | | Branch if we have enough instructions so that it makes sense. Also remove branches if they don't make sense. Patch by: Christian König Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Christian König <deathsimple@vodafone.de> llvm-svn: 170592
* R600: New control flow for SI v2Tom Stellard2012-12-1914-385/+1500
| | | | | | | | | | | | | | | | | | | | This patch replaces the control flow handling with a new pass which structurize the graph before transforming it to machine instruction. This has a couple of different advantages and currently fixes 20 piglit tests without a single regression. It is now a general purpose transformation that could be not only be used for SI/R6xx, but also for other hardware implementations that use a form of structurized control flow. v2: further cleanup, fixes and documentation Patch by: Christian König Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 170591
* Split out abbreviations for the skeleton info from the rest ofEric Christopher2012-12-192-19/+63
| | | | | | the abbreviations. Part of implementing split dwarf. llvm-svn: 170589
* Remove the explicit MachineInstrBuilder(MI) constructor.Jakob Stoklund Olesen2012-12-196-34/+34
| | | | | | | | | | | | | Use the version that also takes an MF reference instead. It would technically be possible to extract an MF reference from the MI as MI->getParent()->getParent(), but that would not work for MIs that are not inserted into any basic block. Given the reasonably small number of places this constructor was used at all, I preferred the compile time check to a run time assertion. llvm-svn: 170588
* Fix a bug that was found by building clang with -fsanitize.Nadav Rotem2012-12-191-1/+6
| | | | | | | | | I introduced it in r166785. PR14291. If TD is unavailable use getScalarSizeInBits, but don't optimize pointers or vectors of pointers. llvm-svn: 170586
* LLVM sdisel normalize bit extraction of the form:Evan Cheng2012-12-191-2/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ((x & 0xff00) >> 8) << 2 to (x >> 6) & 0x3fc This is general goodness since it folds a left shift into the mask. However, the trailing zeros in the mask prevents the ARM backend from using the bit extraction instructions. And worse since the mask materialization may require an addition instruction. This comes up fairly frequently when the result of the bit twiddling is used as memory address. e.g. = ptr[(x & 0xFF0000) >> 16] We want to generate: ubfx r3, r1, #16, #8 ldr.w r3, [r0, r3, lsl #2] vs. mov.w r9, #1020 and.w r2, r9, r1, lsr #14 ldr r2, [r0, r2] Add a late ARM specific isel optimization to ARMDAGToDAGISel::PreprocessISelDAG(). It folds the left shift to the 'base + offset' address computation; change the mask to one which doesn't have trailing zeros and enable the use of ubfx. Note the optimization has to be done late since it's target specific and we don't want to change the DAG normalization. It's also fairly restrictive as shifter operands are not always free. It's only done for lsh 1 / 2. It's known to be free on some cpus and they are most common for address computation. This is a slight win for blowfish, rijndael, etc. rdar://12870177 llvm-svn: 170581
* Remove edis - the enhanced disassembler. Fixes PR14654.Roman Divacky2012-12-1925-2244/+4
| | | | llvm-svn: 170578
* Transform (x&C)>V into (x&C)!=0 where possiblePaul Redmond2012-12-192-37/+10
| | | | | | | | | | | | When the least bit of C is greater than V, (x&C) must be greater than V if it is not zero, so the comparison can be simplified. Although this was suggested in Target/X86/README.txt, it benefits any architecture with a directly testable form of AND. Patch by Kevin Schoedel llvm-svn: 170576
* PowerPC: Expand VSELECT nodes.Benjamin Kramer2012-12-191-0/+1
| | | | | | | | There's probably a better expansion for those nodes than the default for altivec, but this is better than crashing. VSELECTs occur in loop vectorizer output. llvm-svn: 170551
* Change AsmOperandInfo::ConstraintVT to MVT, instead of EVT.Patrik Hagglund2012-12-193-13/+31
| | | | | | Accordingly, add MVT::getVT. llvm-svn: 170550
* Revert 170545 while I debug the ppc failures.Rafael Espindola2012-12-191-25/+10
| | | | llvm-svn: 170547
* Add r170095 back.Rafael Espindola2012-12-191-10/+25
| | | | | | | | | | | | | | | | | | | | | | | I cannot reproduce it the failures locally, so I will keep an eye at the ppc bots. This patch does add the change to the "Disassembly of section" message, but that is not what was failing on the bots. Original message: Add a funciton to get the segment name of a section. On MachO, sections also have segment names. When a tool looking at a .o file prints a segment name, this is what they mean. In reality, a .o has only one anonymous, segment. This patch adds a MachO only function to fetch that segment name. I named it getSectionFinalSegmentName since the main use for the name seems to be infor the linker with segment this section should go to. The patch also changes MachOObjectFile::getSectionName to return just the section name instead of computing SegmentName,SectionName. llvm-svn: 170545
* [msan] Add track-origins argument to the pass constructor.Evgeniy Stepanov2012-12-191-24/+31
| | | | llvm-svn: 170544
* Split the usage of 'EVT PartVT' into 'MVT PartVT' and 'EVT PartEVT'.Patrik Hagglund2012-12-191-38/+38
| | | | llvm-svn: 170540
* Change RegVT in BitTestBlock and RegsForValue, to contain MVTs,Patrik Hagglund2012-12-192-14/+13
| | | | | | instead of EVTs. llvm-svn: 170538
* Change TargetLowering::getTypeForExtArgOrReturn to take and returnPatrik Hagglund2012-12-193-7/+6
| | | | | | MVTs, instead of EVTs. llvm-svn: 170537
* Change a parameter of TargetLowering::getVectorTypeBreakdown to MVT,Patrik Hagglund2012-12-192-14/+19
| | | | | | from EVT. llvm-svn: 170536
* Change TargetLowering::RegisterTypeForVT to contain MVTs, instead ofPatrik Hagglund2012-12-196-20/+20
| | | | | | EVTs. llvm-svn: 170535
* Change TargetLowering::TransformToType to contain MVTs, instead ofPatrik Hagglund2012-12-191-4/+4
| | | | | | EVTs. llvm-svn: 170534
* Change TargetLowering::findRepresentativeClass to take an MVT, insteadPatrik Hagglund2012-12-195-8/+8
| | | | | | of EVT. llvm-svn: 170532
* [msan] Heuristically instrument unknown intrinsics.Evgeniy Stepanov2012-12-191-1/+143
| | | | | | | | | | | | This changes adds shadow and origin propagation for unknown intrinsics by examining the arguments and ModRef behaviour. For now, only 3 classes of intrinsics are handled: - those that look like simple SIMD store - those that look like simple SIMD load - those that don't have memory effects and look like arithmetic/logic/whatever operation on simple types. llvm-svn: 170530
* Change TargetLowering::getTypeToPromoteTo to take and return MVTs,Patrik Hagglund2012-12-192-9/+9
| | | | | | instead of EVTs. llvm-svn: 170529
* LoopVectorize: Make iteration over induction variables not depend on pointer ↵Benjamin Kramer2012-12-191-4/+4
| | | | | | | | | | values. MapVector is a bit heavyweight, but I don't see a simpler way. Also the InductionList is unlikely to be large. This should help 3-stage selfhost compares (PR14647). llvm-svn: 170528
* Change TargetLowering::isCondCodeLegal to take an MVT, instead of EVT.Patrik Hagglund2012-12-192-12/+15
| | | | llvm-svn: 170524
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