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| author | Tom Stellard <thomas.stellard@amd.com> | 2012-12-19 22:10:34 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2012-12-19 22:10:34 +0000 |
| commit | 1c315d54111faee947f5bd7ca3d4ffbeb89a003e (patch) | |
| tree | 93ab3d91e7b093ca3d294218aca4b83b512530f8 /llvm/lib | |
| parent | e7b907d85c194778ef68b40e2339647627dea4ba (diff) | |
| download | bcm5719-llvm-1c315d54111faee947f5bd7ca3d4ffbeb89a003e.tar.gz bcm5719-llvm-1c315d54111faee947f5bd7ca3d4ffbeb89a003e.zip | |
R600: Remove unecessary VREG alignment.
Unlike SGPRs VGPRs doesn't need to be aligned.
Patch by: Christian König
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Christian König <deathsimple@vodafone.de>
llvm-svn: 170593
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/R600/SIRegisterInfo.td | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/Target/R600/SIRegisterInfo.td b/llvm/lib/Target/R600/SIRegisterInfo.td index e52311ab8a9..c3f136191a6 100644 --- a/llvm/lib/Target/R600/SIRegisterInfo.td +++ b/llvm/lib/Target/R600/SIRegisterInfo.td @@ -105,15 +105,15 @@ def VGPR_32 : RegisterClass<"AMDGPU", [f32, i32], 32, // VGPR 64-bit registers def VGPR_64 : RegisterTuples<[low, high], - [(add (decimate VGPR_32, 2)), - (add (decimate (rotl VGPR_32, 1), 2))]>; + [(add VGPR_32), + (add (rotl VGPR_32, 1))]>; // VGPR 128-bit registers def VGPR_128 : RegisterTuples<[sel_x, sel_y, sel_z, sel_w], - [(add (decimate VGPR_32, 4)), - (add (decimate (rotl VGPR_32, 1), 4)), - (add (decimate (rotl VGPR_32, 2), 4)), - (add (decimate (rotl VGPR_32, 3), 4))]>; + [(add VGPR_32), + (add (rotl VGPR_32, 1)), + (add (rotl VGPR_32, 2)), + (add (rotl VGPR_32, 3))]>; // Register class for all scalar registers (SGPRs + Special Registers) def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32, |
