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* Allow NULL LoopPassManager argument in UnrollLoop. PR12734.Andrew Trick2012-05-082-20/+26
| | | | llvm-svn: 156358
* Extract methods for joining physregs.Jakob Stoklund Olesen2012-05-081-77/+103
| | | | | | No functional change. llvm-svn: 156345
* Naming convention and whitespace. No functional change.Jakob Stoklund Olesen2012-05-071-68/+67
| | | | llvm-svn: 156342
* Coalesce subreg-subreg copies.Jakob Stoklund Olesen2012-05-071-14/+25
| | | | | | | | | | | | | | | | | At least some of them: %vreg1:sub_16bit = COPY %vreg2:sub_16bit; GR64:%vreg1, GR32: %vreg2 Previously, we couldn't figure out that the above copy could be eliminated by coalescing %vreg2 with %vreg1:sub_32bit. The new getCommonSuperRegClass() hook makes it possible. This is not very useful yet since the unmodified part of the destination register usually interferes with the source register. The coalescer needs to understand sub-register interference checking first. llvm-svn: 156334
* Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().Jakob Stoklund Olesen2012-05-0728-47/+69
| | | | | | | | | | | | | The getPointerRegClass() hook can return register classes that depend on the calling convention of the current function (ptr_rc_tailcall). So far, we have been able to infer the calling convention from the subtarget alone, but as we add support for multiple calling conventions per target, that no longer works. Patch by Yiannis Tsiouris! llvm-svn: 156328
* Fix bug in TRI::getCommonSuperRegClass().Jakob Stoklund Olesen2012-05-071-0/+1
| | | | | | Test cases for this code are coming. It is not used for anything yet. llvm-svn: 156327
* Teach DAG combine to fold x-x to 0.0 when unsafe FP math is enabled.Owen Anderson2012-05-071-0/+4
| | | | llvm-svn: 156324
* Teach reassociate to commute FMul's and FAdd's in order to canonicalize the ↵Owen Anderson2012-05-071-4/+28
| | | | | | order of their operands across instructions. This allows for greater CSE opportunities. llvm-svn: 156323
* Make IntelJITEvents and OProfileJIT as optional libraries and addPreston Gurd2012-05-072-2/+2
| | | | | | | | | | | | optional library support to the llvm-build tool: - Add new command line parameter to llvm-build: “--enable-optional-libraries” - Add handing of new llvm-build library type “OptionalLibrary” - Update Cmake and automake build systems to pass correct flags to llvm-build based on configuration Patch by Dan Malea! llvm-svn: 156319
* Add TRI::getCommonSuperRegClass().Jakob Stoklund Olesen2012-05-071-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | This function is a generalization of getMatchingSuperRegClass() to the symmetric case where both sides are using a sub-register index. It will find a super-register class and sub-register indexes that make this diagram commute: PreA SuperRC ----------> RCA | | | | PreB | | SubA | | | | V V RCB ----------> SubRC SubB This can be used to coalesce copies like: %vreg1:sub16 = COPY %vreg2:sub16; GR64:%vreg1, GR32: %vreg2 llvm-svn: 156317
* Fix a regression from r147481. This combine should only happen if there is aChad Rosier2012-05-071-10/+12
| | | | | | | single use. rdar://11360370 llvm-svn: 156316
* Don't assume size_t is unsigned long long.Matt Beaumont-Gay2012-05-071-3/+1
| | | | | | Fixes a -Woverflow warning from gcc when building for 32-bit platforms. llvm-svn: 156313
* X86: optimization for -(x != 0)Manman Ren2012-05-072-0/+22
| | | | | | | | | | | | | | | | | This patch will optimize -(x != 0) on X86 FROM cmpl $0x01,%edi sbbl %eax,%eax notl %eax TO negl %edi sbbl %eax %eax In order to generate negl, I added patterns in Target/X86/X86InstrCompiler.td: def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>; rdar: 10961709 llvm-svn: 156312
* Add support for the 'x' constraint.Eric Christopher2012-05-071-1/+8
| | | | | | Patch by Jack Carter. llvm-svn: 156295
* Add support for the 'l' constraint.Eric Christopher2012-05-071-0/+7
| | | | | | Patch by Jack Carter. llvm-svn: 156294
* Add support for the 'c' constraint.Eric Christopher2012-05-071-1/+13
| | | | | | Patch by Jack Carter. llvm-svn: 156293
* Add support for the 'P' constraint.Eric Christopher2012-05-071-0/+11
| | | | | | Patch by Jack Carter. llvm-svn: 156292
* Fix some issues in the f16c instructions.Craig Topper2012-05-071-11/+9
| | | | llvm-svn: 156287
* Add support for the 'O' constraint.Eric Christopher2012-05-071-0/+11
| | | | | | Patch by Jack Carter. llvm-svn: 156285
* Add support for the 'N' inline asm constraint.Eric Christopher2012-05-071-0/+11
| | | | | | Patch by Jack Carter. llvm-svn: 156284
* Add support for the 'L' inline asm constraint.Eric Christopher2012-05-071-0/+11
| | | | | | Patch by Jack Carter. llvm-svn: 156283
* Add support for the inline asm constraint 'K'.Eric Christopher2012-05-071-0/+11
| | | | llvm-svn: 156282
* Add SSE4A MOVNTSS/MOVNTSD instructions.Craig Topper2012-05-071-0/+14
| | | | llvm-svn: 156281
* Support the 'J' constraint.Eric Christopher2012-05-071-0/+11
| | | | | | Patch by Jack Carter. llvm-svn: 156280
* Add support for the 'I' inline asm constraint. Also add testsEric Christopher2012-05-072-0/+48
| | | | | | | | from the previous 2 patches. Patch by Jack Carter. llvm-svn: 156279
* Allow 64 bit integer values in gpu registers if arch and abi are 64 bit.Eric Christopher2012-05-071-2/+4
| | | | | | Patch by Jack Carter. llvm-svn: 156278
* When using inline asm constraints representingEric Christopher2012-05-071-1/+1
| | | | | | | | | non-floating point general registers allow 8 and 16-bit elements. Patch by Jack Carter. llvm-svn: 156277
* Use MVT instead of EVT as the argument to all the shuffle decode functions. ↵Craig Topper2012-05-063-35/+33
| | | | | | Simplify some of the decode functions. llvm-svn: 156268
* Add VPERMQ/VPERMPD to the list of target specific shuffles that can be ↵Craig Topper2012-05-061-0/+6
| | | | | | looked through for DAG combine purposes. llvm-svn: 156266
* Add shuffle decode support for VPERMQ/VPERMPD.Craig Topper2012-05-063-0/+22
| | | | llvm-svn: 156265
* make SourceMgr tolerate empty SMLoc()'s better.Chris Lattner2012-05-061-45/+54
| | | | llvm-svn: 156260
* Switch the select to branch transformation on by default.Benjamin Kramer2012-05-061-3/+4
| | | | | | | | | The primitive conservative heuristic seems to give a slight overall improvement while not regressing stuff. Make it available to wider testing. If you notice any speed regressions (or significant code size regressions) let me know! llvm-svn: 156258
* Remove trailing spaces.Jakub Staszak2012-05-061-60/+60
| | | | llvm-svn: 156257
* Unix/Process.inc: Give more useful random seed to srand. Workaround for PR12743.NAKAMURA Takumi2012-05-061-1/+14
| | | | llvm-svn: 156252
* Support/Process: Move llvm::sys::Process::GetRandomNumber() from Process.cpp ↵NAKAMURA Takumi2012-05-062-10/+9
| | | | | | | to Unix/Process.inc. FIXME: GetRandomNumber() is not implemented in Win32. llvm-svn: 156251
* reapply my patch, with a fix for an off-by-one error. Turned out to be a lotChris Lattner2012-05-051-12/+18
| | | | | | of work for a drive-by fix :) llvm-svn: 156246
* revert my patches, which are causing problems.Chris Lattner2012-05-051-18/+12
| | | | llvm-svn: 156245
* refactor some code to expose column numbers more and make diagnostic ↵Chris Lattner2012-05-051-12/+18
| | | | | | printing slightly more efficient. llvm-svn: 156243
* Nuke a few dead remnants of the CBE.Jim Grosbach2012-05-053-46/+0
| | | | llvm-svn: 156241
* [Support] Add missing include.Daniel Dunbar2012-05-051-1/+2
| | | | llvm-svn: 156240
* [Support] Fix up comments.Daniel Dunbar2012-05-051-5/+3
| | | | llvm-svn: 156239
* [Support] Rewrite sys::fs::unique_file to not be stupid with /dev/urandom.Daniel Dunbar2012-05-051-19/+5
| | | | | | | | - Just use sys::Process::GetRandomNumber instead of having two poor implementations. - This is ~70 times (!) faster on my OS X machine. llvm-svn: 156238
* [Support] Add sys::Process::GetRandomNumber().Daniel Dunbar2012-05-051-0/+9
| | | | | | - Primitive API, but we rarely have need for random numbers. llvm-svn: 156237
* CodeGenPrepare: Add a transform to turn selects into branches in some cases.Benjamin Kramer2012-05-051-0/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This came up when a change in block placement formed a cmov and slowed down a hot loop by 50%: ucomisd (%rdi), %xmm0 cmovbel %edx, %esi cmov is a really bad choice in this context because it doesn't get branch prediction. If we emit it as a branch, an out-of-order CPU can do a better job (if the branch is predicted right) and avoid waiting for the slow load+compare instruction to finish. Of course it won't help if the branch is unpredictable, but those are really rare in practice. This patch uses a dumb conservative heuristic, it turns all cmovs that have one use and a direct memory operand into branches. cmovs usually save some code size, so we disable the transform in -Os mode. In-Order architectures are unlikely to benefit as well, those are included in the "predictableSelectIsExpensive" flag. It would be better to reuse branch probability info here, but BPI doesn't support select instructions currently. It would make sense to use the same heuristics as the if-converter pass, which does the opposite direction of this transform. Test suite shows a small improvement here and there on corei7-level machines, but the actual results depend a lot on the used microarchitecture. The transformation is currently disabled by default and available by passing the -enable-cgp-select2branch flag to the code generator. Thanks to Chandler for the initial test case to him and Evan Cheng for providing me with comments and test-suite numbers that were more stable than mine :) llvm-svn: 156234
* Add a new target hook "predictableSelectIsExpensive".Benjamin Kramer2012-05-053-0/+7
| | | | | | | | | | | This will be used to determine whether it's profitable to turn a select into a branch when the branch is likely to be predicted. Currently enabled for everything but Atom on X86 and Cortex-A9 devices on ARM. I'm not entirely happy with the name of this flag, suggestions welcome ;) llvm-svn: 156233
* NVPTX: Initialize the UseF32FTZ flag.Benjamin Kramer2012-05-051-0/+2
| | | | llvm-svn: 156232
* Small fix in InstCombineCasts.cpp. Restored "alloca + bitcast" reducing for ↵Stepan Dyatkovskiy2012-05-051-1/+1
| | | | | | | | case when alloca's size is calculated within the "add/sub/... nsw". Also added fix to 2011-06-13-nsw-alloca.ll test. llvm-svn: 156231
* Typo.Eric Christopher2012-05-051-1/+1
| | | | llvm-svn: 156226
* Make sure findRepresentativeClass picks the widest super-register.Jakob Stoklund Olesen2012-05-041-6/+10
| | | | | | | | We want the representative register class to contain the largest super-registers available. This makes the function less sensitive to the register class numbering. llvm-svn: 156220
* Remove extra comma in debug output.Jakob Stoklund Olesen2012-05-041-1/+1
| | | | llvm-svn: 156219
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