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* TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine ↵Andrew Trick2012-09-182-2/+11
| | | | | | model. llvm-svn: 164092
* Mark unimplemented copy constructors and copy assignment operators as ↵Craig Topper2012-09-185-11/+10
| | | | | | LLVM_DELETED_FUNCTION. llvm-svn: 164090
* Use vld1 / vst2 for unaligned v2f64 load / store. e.g. Use vld1.16 for 2-byteEvan Cheng2012-09-182-5/+42
| | | | | | | | | aligned address. Based on patch by David Peixotto. Also use vld1.64 / vst1.64 with 128-bit alignment to take advantage of alignment hints. rdar://12090772, rdar://12238782 llvm-svn: 164089
* Fix some funky indentation.Evan Cheng2012-09-181-18/+17
| | | | llvm-svn: 164087
* PGO: preserve branch-weight metadata when simplifying Switch to a sub, an icmpManman Ren2012-09-181-1/+38
| | | | | | and a conditional branch; also when removing dead cases from a switch. llvm-svn: 164084
* PGO: preserve branch-weight metadata when simplifying SwitchManman Ren2012-09-171-0/+15
| | | | | | | Hanlde the case when we split the default edge if the default target has "icmp" and unconditinal branch. llvm-svn: 164076
* Merge into undefined lanes under -new-coalescer.Jakob Stoklund Olesen2012-09-172-2/+120
| | | | | | | | | | | | | | | | | Add LIS::pruneValue() and extendToIndices(). These two functions are used by the register coalescer when merging two live ranges requires more than a trivial value mapping as supported by LiveInterval::join(). The pruneValue() function can remove the part of a value number that is going to conflict in join(). Afterwards, extendToIndices can restore the live range, using any new dominating value numbers and updating the SSA form. Use this complex value mapping to support merging a register into a vector lane that has a conflicting value, but the clobbered lane is undef. llvm-svn: 164074
* Stop adding <imp-def> operands when expanding REG_SEQUENCE.Jakob Stoklund Olesen2012-09-171-4/+0
| | | | | | | | | | These extra operands are not needed by register allocators using VirtRegRewriter, and RAFast don't need them any longer. By omitting the <imp-def> operands, it becomes possible for the new register coalescer to track which lanes are valid and which are undef. llvm-svn: 164073
* Revert r164061-r164067. Most of the new subtarget emitter.Andrew Trick2012-09-174-172/+22
| | | | | | | I have to work out the Target/CodeGen header dependencies before putting this back. llvm-svn: 164072
* PGO: preserve branch-weight metadata when simplifying SwitchOnSelect.Manman Ren2012-09-171-5/+28
| | | | llvm-svn: 164068
* InitMCProcessorAndrew Trick2012-09-171-14/+15
| | | | llvm-svn: 164066
* TargetSchedModel API. Implement latency lookup, disabled.Andrew Trick2012-09-173-8/+148
| | | | llvm-svn: 164065
* TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine ↵Andrew Trick2012-09-172-2/+11
| | | | | | model. llvm-svn: 164061
* Add some cases to x86 OptimizeCompare to handle DEC and INC, too.Jan Wen Voung2012-09-171-4/+14
| | | | | | While we are setting the earlier def to true, also make it live. llvm-svn: 164056
* PGO: preserve branch-weight metadata when simplifying two branches with a commonManman Ren2012-09-171-0/+27
| | | | | | destination in SimplifyCondBranchToCondBranch. llvm-svn: 164054
* Make sure there is enough room for RA. getStackSize needs to be cleaned up butAkira Hatanaka2012-09-171-0/+4
| | | | | | | | we will do that when we implement the full save/restore. Patch by Reed Kotler. llvm-svn: 164051
* Increase the static sizes of some SmallSets. finalizeBundle() is very ↵Michael Ilseman2012-09-171-4/+4
| | | | | | frequently called for some backends, and growing into an std::set is overkill for these numbers. llvm-svn: 164044
* whitespaceMichael Ilseman2012-09-171-1/+1
| | | | llvm-svn: 164043
* Fix PR13859Michael Liao2012-09-171-6/+7
| | | | | | | - Preserve the original NOutVT during casting from vector to integer by extracting vector elements. llvm-svn: 164042
* s/__llvm_gcov_flush/__gcov_flush/gBill Wendling2012-09-171-4/+4
| | | | llvm-svn: 164040
* LLVM_ATTRIBUTE_USED forces emission of a function. To silence unused ↵Benjamin Kramer2012-09-171-2/+2
| | | | | | function warnings use LLVM_ATTRIBUTE_UNUSED. llvm-svn: 164036
* NewSROA: Provide a full set of operator< for ByteRanges.Benjamin Kramer2012-09-171-2/+7
| | | | | | MSVC8 won't compile lower_bound if one is missing. llvm-svn: 164035
* Fix a few vars that can end up being used without initialization.Axel Naumann2012-09-172-2/+2
| | | | | | The cases where no initialization happens should still be checked for logic flaws. llvm-svn: 164032
* Removed the VMLxForwarding feature for the Cortex-A15 target.Silviu Baranga2012-09-171-2/+1
| | | | llvm-svn: 164030
* Add a MachinePostDominator passTom Stellard2012-09-173-0/+57
| | | | | | This is used in the AMDIL and R600 backends. llvm-svn: 164029
* Disable the protection from escaped allocas in an attempt to find violating ↵Nadav Rotem2012-09-171-2/+1
| | | | | | passes. This may break the buildbots. I plan to revert it in a few hours. llvm-svn: 164024
* Refactor the SROA visitors for partitioning an alloca and buildingChandler Carruth2012-09-161-24/+29
| | | | | | | | | | | | | | | | | | | | | partition use lists a bit. No functionality changed. These visitors are actually visiting a tuple of a Use and an offset into the alloca. However, we use the InstVisitor to handle the dispatch over the users, and so the Use and Offset are stored in class member variables and set just before each call to visit(). This is fairly awkward and makes the functions a bit harder to read, but its the only real option we have until InstVisitor can be rewritten to use variadic templates. However, this pattern shouldn't be followed on the helper member functions where there is no interface constraint from the visitor. We already were passing the instruction as a normal parameter rather than use the Use to get at it, start passing the offset as well. This will become more important in subsequent patches as the offset will in some cases change while visiting a single instruction. llvm-svn: 164003
* Change unsigned to uint32_t to match base class declaration and other targets.Craig Topper2012-09-162-2/+2
| | | | llvm-svn: 164001
* Fix bad comment. No functional change.Craig Topper2012-09-161-1/+1
| | | | llvm-svn: 164000
* The PMOVZXWD family of functions had patterns extends narrow vector types to ↵Nadav Rotem2012-09-161-0/+24
| | | | | | | | | | | wide vector types. It had patterns for zext-loading and extending. This commit adds patterns for loading a wide type, performing a bitcast, and extending. This is an odd pattern, but it is commonly used when writing code with intrinsics. rdar://11897677 llvm-svn: 163995
* Add alternative coalescing algorithm under a flag.Jakob Stoklund Olesen2012-09-161-0/+478
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The live range of an SSA value forms a sub-tree of the dominator tree. That means the live ranges of two values overlap if and only if the def of one value lies within the live range of the other. This can be used to simplify the interference checking a bit: Visit each def in the two registers about to be joined. Check for interference against the value that is live in the other register at the def point only. It is not necessary to scan the set of overlapping live ranges, this interference check can be done while computing the value mapping required for the final live range join. The new algorithm is prepared to handle more complicated conflict resolution - We can allow overlapping live ranges with different values as long as the differing lanes are undef or unused in the other register. The implementation in this patch doesn't do that yet, it creates code that is nearly identical to the old algorithm's, except: - The new stripCopies() function sees through multiple copies while the old RegistersDefinedFromSameValue() only can handle one. - There are a few rare cases where the new algorithm can erase an IMPLICIT_DEF instuction that RegistersDefinedFromSameValue() couldn't handle. llvm-svn: 163991
* Use LLVM_DELETED_FUNCTION in place of 'DO NOT IMPLEMENT' comments.Craig Topper2012-09-1514-38/+41
| | | | llvm-svn: 163974
* Remove unused private fields to silence -Wunused-private-field.Craig Topper2012-09-151-9/+6
| | | | llvm-svn: 163973
* Don't depend on kill flags in removeCopyByCommutingDef().Jakob Stoklund Olesen2012-09-151-1/+1
| | | | | | | Kill flags are removed more and more aggressively during the register allocation passes, it is better to get information from LiveIntervals. llvm-svn: 163972
* Use LLVM_DELETED_FUNCTION in place of 'DO NOT IMPLEMENT' comments.Craig Topper2012-09-151-2/+2
| | | | llvm-svn: 163970
* Disable new sroa now that all buildbots have tested it.Benjamin Kramer2012-09-151-1/+1
| | | | | | | | | | | | | | | | | What we have so far: - Some clang test failures (these were known already) - Perf results are mixed, some big regressions http://llvm.org/perf/db_default/v4/nts/3844 http://llvm.org/perf/db_default/v4/nts/3845 bullet suffers a lot. matmul is interesting: slower scalar code, faster with -vectorize. - Some dragonegg selfhost bots crash in SROA during selfhost now http://lab.llvm.org:8011/builders/dragonegg-x86_64-linux-gcc-4.6-self-host-checks/builds/1632 http://lab.llvm.org:8011/builders/dragonegg-x86_64-linux-gcc-4.5-self-host/builds/1891 llvm-svn: 163968
* X86: Emitting x87 fsin/fcos for sinf/cosf is not safe without unsafe fp math.Benjamin Kramer2012-09-151-0/+2
| | | | | | This was only an issue if sse is disabled. llvm-svn: 163967
* Port the SSAUpdater-based promotion logic from the old SROA pass to theChandler Carruth2012-09-152-14/+167
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | new one, and add support for running the new pass in that mode and in that slot of the pass manager. With this the new pass can completely replace the old one within the pipeline. The strategy for enabling or disabling the SSAUpdater logic is to do it by making the requirement of the domtree analysis optional. By default, it is required and we get the standard mem2reg approach. This is usually the desired strategy when run in stand-alone situations. Within the CGSCC pass manager, we disable requiring of the domtree analysis and consequentially trigger fallback to the SSAUpdater promotion. In theory this would allow the pass to re-use a domtree if one happened to be available even when run in a mode that doesn't require it. In practice, it lets us have a single pass rather than two which was simpler for me to wrap my head around. There is a hidden flag to force the use of the SSAUpdater code path for the purpose of testing. The primary testing strategy is just to run the existing tests through that path. One notable difference is that it has custom code to handle lifetime markers, and one of the tests has been enhanced to exercise that code. This has survived a bootstrap and the test suite without serious correctness issues, however my run of the test suite produced *very* alarming performance numbers. I don't entirely understand or trust them though, so more investigation is on-going. To aid my understanding of the performance impact of the new SROA now that it runs throughout the optimization pipeline, I'm enabling it by default in this commit, and will disable it again once the LNT bots have picked up one iteration with it. I want to get those bots (which are much more stable) to evaluate the impact of the change before I jump to any conclusions. NOTE: Several Clang tests will fail because they run -O3 and check the result's order of output. They'll go back to passing once I disable it again. llvm-svn: 163965
* Remove aligned/unaligned load/store fragments defined in MipsInstrInfo.td andAkira Hatanaka2012-09-156-146/+52
| | | | | | | | | | use load/store fragments defined in TargetSelectionDAG.td in place of them. Unaligned loads/stores are either expanded or lowered to target-specific nodes, so instruction selection should see only aligned load/store nodes. No changes in functionality. llvm-svn: 163960
* Handled unaligned load/stores properly in Mips16 Akira Hatanaka2012-09-151-2/+7
| | | | | | Patch by Reed Kotler. llvm-svn: 163956
* PGO: preserve branch-weight metadata when simplifying two branches with a commonManman Ren2012-09-151-111/+42
| | | | | | | | | | | | | | | | destination. Updated previous implementation to fix a case not covered: // PBI: br i1 %x, TrueDest, BB // BI: br i1 %y, TrueDest, FalseDest The other case was handled correctly. // PBI: br i1 %x, BB, FalseDest // BI: br i1 %y, TrueDest, FalseDest Also tried to use 64-bit arithmetic instead of APInt with scale to simplify the computation. Let me know if you have other opinions about this. llvm-svn: 163954
* Remove comment.Bill Wendling2012-09-141-1/+1
| | | | llvm-svn: 163945
* PGO: preserve branch-weight metadata when simplifying a switch with a singleManman Ren2012-09-142-2/+33
| | | | | | case to a conditional branch and when removing dead cases. llvm-svn: 163942
* Stylistic and 80-col fixesEvan Cheng2012-09-142-8/+4
| | | | llvm-svn: 163940
* TargetSchedModel interface. To be implemented...Andrew Trick2012-09-143-0/+39
| | | | llvm-svn: 163934
* Define MC data tables for the new scheduling machine model.Andrew Trick2012-09-141-5/+5
| | | | llvm-svn: 163933
* Review feedback from Duncan Sands. Alphabetize includes and simplifyAlex Rosenberg2012-09-141-3/+3
| | | | | | lit config. llvm-svn: 163928
* Try to fix the bots by detecting inconsistant branch-weight metadata.Manman Ren2012-09-141-4/+10
| | | | llvm-svn: 163926
* Implement getNumLDMAddresses and expose through ARMBaseInstrInfo.Andrew Trick2012-09-142-0/+34
| | | | llvm-svn: 163922
* Cortex-A9 instruction-level scheduling machine model.Andrew Trick2012-09-141-3/+594
| | | | | | | | | | | | | | | | | | | | This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
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