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* [APInt] Use conditional operator to simplify some code. NFCCraig Topper2017-04-011-4/+1
| | | | llvm-svn: 299320
* [APInt] Implement flipAllBitsSlowCase with tcComplement. NFCICraig Topper2017-04-011-2/+1
| | | | llvm-svn: 299319
* [APInt] Fix indentation. NFCCraig Topper2017-04-011-8/+8
| | | | llvm-svn: 299318
* [APInt] Implement AndAssignSlowCase using tcAnd. Do the same for Or and Xor. ↵Craig Topper2017-04-011-9/+3
| | | | | | NFCI llvm-svn: 299317
* [APInt] Allow GreatestCommonDivisor to take rvalue inputs efficiently. Use ↵Craig Topper2017-04-011-6/+4
| | | | | | | | | | | | | | | | | | | moves instead of copies in the loop. Summary: GreatestComonDivisor currently makes a copy of both its inputs. Then in the loop we do one move and two copies, plus any allocation the urem call does. This patch changes it to take its inputs by value so that we can do a move of any rvalue inputs instead of copying. Then in the loop we do 3 move assignments and no copies. This way the only possible allocations we have in the loop is from the urem call. Reviewers: dblaikie, RKSimon, hans Reviewed By: dblaikie Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31572 llvm-svn: 299314
* [WASM] Remove other comparison of unsigned expression >= 0.Davide Italiano2017-04-011-3/+3
| | | | | | This should finally fix the GCC 7 build with -Werror. llvm-svn: 299313
* [WASM] Remove a set but never used variable.Davide Italiano2017-04-011-4/+1
| | | | llvm-svn: 299312
* [WASM] Remove an assertion that can never fire.Davide Italiano2017-04-011-2/+2
| | | | | | uint* is by definition always >=0. llvm-svn: 299311
* [AMDGPU] Garbage collect now unused dead code. NFCI.Davide Italiano2017-04-011-10/+0
| | | | llvm-svn: 299310
* [InstSimplify] add constant folding for fdiv/fremSanjay Patel2017-04-011-70/+49
| | | | | | Also, add a helper function so we don't have to repeat this code for each binop. llvm-svn: 299309
* fix formatting; NFCSanjay Patel2017-04-011-34/+35
| | | | llvm-svn: 299307
* [DAGCombiner] enable vector transforms for any/all {sign} bits set/clearSanjay Patel2017-04-011-13/+17
| | | | | | | | The code already allowed vector types in via "isInteger" (which might want a more specific name), so use splat-friendly constant predicates to match those types. llvm-svn: 299304
* NewGVN: Don't try to kill off the stored value of stores whenDaniel Berlin2017-04-011-9/+22
| | | | | | | | | | | | | processing the congruence class of the store. Because we use the stored value of a store as the def, it isn't dead just because it appears as a def when it comes from a store. Note: I have not hit any cases with the memory code as it is where this breaks anything, just because of what memory congruences we actually allow. In a followup that improves memory congruence, this bug actually breaks real stuff (but the verifier catches it). llvm-svn: 299300
* NewGVN: Clean up GVNExpression memory hierarchy, restructure hash ↵Daniel Berlin2017-04-011-16/+8
| | | | | | computation a bit so we don't have to redefine it for loads, stores, and calls llvm-svn: 299299
* NewGVN: Use def_chain iterator in singleReachablePhiPath instead of recursionDaniel Berlin2017-04-011-20/+24
| | | | llvm-svn: 299298
* Move def_chain iterator to MemorySSA.h so it can be reusedDaniel Berlin2017-04-011-36/+0
| | | | llvm-svn: 299297
* MemorySSA: Push const correctness further.Daniel Berlin2017-04-011-8/+10
| | | | llvm-svn: 299295
* MemorySSA: Kill the WalkTargetCache now that we have getBlockDefs.Daniel Berlin2017-04-011-39/+6
| | | | llvm-svn: 299294
* [APInt] Remove the mul/urem/srem/udiv/sdiv functions from the APIntOps ↵Craig Topper2017-04-012-2/+2
| | | | | | namespace. Replace the few usages with calls to the class methods. NFC llvm-svn: 299292
* [DAGCombiner] Fix fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, ↵Craig Topper2017-04-011-1/+1
| | | | | | | | | | B, Mask) to explicitly ensure that only one of the inputs of each shuffle is a zero vector. This can only happen when we have a mix of zero and undef elements and the two vectors have a different arrangement of zeros/undefs. The shuffle should eventually be constant folded to all zeros. Fixes PR32484. llvm-svn: 299291
* Revert "Feature generic option to setup start/stop-after/before"Quentin Colombet2017-04-011-61/+0
| | | | | | | | This reverts commit r299282. Didn't intend to commit this :( llvm-svn: 299288
* Revert "Localizer fun"Quentin Colombet2017-04-013-122/+0
| | | | | | | | This reverts commit r299283. Didn't intend to commit this :( llvm-svn: 299287
* Revert "Instrument SDISel C++ patterns"Quentin Colombet2017-04-013-369/+356
| | | | | | | | This reverts commit r299284. Didn't intend to commit this :( llvm-svn: 299286
* [RegBankSelect] Support REG_SEQUENCE for generic mappingQuentin Colombet2017-04-011-8/+18
| | | | | | | | | | | | | | | | REG_SEQUENCE falls into the same category as COPY for operands mapping: - They don't have MCInstrDesc with register constraints - The input variable could use whatever register classes - It is possible to have register class already assigned to the operands In particular, given REG_SEQUENCE are always target specific because of the subreg indices. Those indices must apply to the register class of the definition of the REG_SEQUENCE and therefore, the target must set a register class to that definition. As a result, the generic code can always use that register class to derive a valid mapping for a REG_SEQUENCE. llvm-svn: 299285
* Instrument SDISel C++ patternsQuentin Colombet2017-04-013-356/+369
| | | | llvm-svn: 299284
* Localizer funQuentin Colombet2017-04-013-0/+122
| | | | | | WIP llvm-svn: 299283
* Feature generic option to setup start/stop-after/beforeQuentin Colombet2017-04-011-0/+61
| | | | | | | | | | | | | This patch refactors the code used in llc such that all the users of the addPassesToEmitFile API have access to a homogeneous way of handling start/stop-after/before options right out of the box. Previously each user would have needed to duplicate this logic and set up its own options. NFC llvm-svn: 299282
* Reduce the number of times we query the subtarget for the same information.Eric Christopher2017-03-311-5/+4
| | | | llvm-svn: 299278
* Small cleanup to remove extraneous cast.Eric Christopher2017-03-311-2/+1
| | | | llvm-svn: 299277
* [APInt] Fix bugs in isShiftedMask to match behavior of the similar function ↵Craig Topper2017-03-311-1/+1
| | | | | | | | | | in MathExtras.h This removes a parameter from the routine that was responsible for a lot of the issue. It was a bit count that had to be set to the BitWidth of the APInt and would get passed to getLowBitsSet. This guaranteed the call to getLowBitsSet would create an all ones value. This was then compared to (V | (V-1)). So the only shifted masks we detected had to have the MSB set. The one in tree user is a transform in InstCombine that never fires due to earlier transforms covering the case better. I've submitted a patch to remove it completely, but for now I've just adapted it to the new interface for isShiftedMask. llvm-svn: 299273
* Add virtual destructor to WasmYAML::Section or avoid memory leakDerek Schuff2017-03-311-0/+9
| | | | | | | | | | Tested locally with -DLLVM_USE_SANITIZER=Address Differential Revision: https://reviews.llvm.org/D31551 Patch by Sam Clegg llvm-svn: 299270
* LTO: call getRealLinkageName on IRNames before feeding to getGUIDBob Haarman2017-03-311-3/+5
| | | | | | | | | | | | | | Summary: GlobalValue has two getGUID methods: an instance method and a static method. The static method takes a string, which is expected to be what GlobalValue::getRealLinkageName() would return. In LTO.cpp, we were not doing this consistently, sometimes passing an IR name instead. This change makes it so that we call getRealLinkageName() first, making the static getGUID return value consistent with the instance method. Without this change, compiling FileCheck with ThinLTO on Windows fails with numerous undefined symbol errors. With the change, it builds successfully. Reviewers: pcc, rnk Reviewed By: pcc Subscribers: tejohnson, mehdi_amini, llvm-commits Differential Revision: https://reviews.llvm.org/D31444 llvm-svn: 299268
* [InstCombine] When adding an Instruction and its Users to the worklist at ↵Craig Topper2017-03-311-2/+2
| | | | | | | | the same time, make sure we put the Users in first. Then put in the instruction. This way we ensure we immediately revisit the instruction and do any additional optimizations before visiting the users. Otherwise we might visit the users, then the instruction, then users again, then instruction again. llvm-svn: 299267
* [DAGCombiner] refactor and/or-of-setcc to get rid of duplicated code; NFCISanjay Patel2017-03-311-90/+39
| | | | llvm-svn: 299266
* [Hexagon] Remove unused variablesKrzysztof Parzyszek2017-03-313-18/+4
| | | | | | Found by PVS-Studio. Fixes llvm.org/PR31676. llvm-svn: 299262
* [Hexagon] Fix typo in HexagonEarlyIfCConv.cppKrzysztof Parzyszek2017-03-311-1/+1
| | | | | | Found by PVS-Studio. Fixes llvm.org/PR32480. llvm-svn: 299258
* Fix APFloat mod (committing for simonbyrne)Stephen Canon2017-03-311-33/+9
| | | | | | | | The previous version was prone to intermediate rounding or overflow. Differential Revision: https://reviews.llvm.org/D29346 llvm-svn: 299256
* [DAGCombiner] add fold for 'All sign bits set?'Sanjay Patel2017-03-311-2/+4
| | | | | | | | | | (and (setlt X, 0), (setlt Y, 0)) --> (setlt (and X, Y), 0) We have 7 similar folds, but this one got away. The fact that the x86 test with a branch didn't change is probably a separate bug. We may also be missing this and the related folds in instcombine. llvm-svn: 299252
* [AMDGPU] Remove assumption that vector and scalar types do not aliasStanislav Mekhanoshin2017-03-311-8/+0
| | | | | | Differential Revision: https://reviews.llvm.org/D31547 llvm-svn: 299250
* [APInt] Remove shift functions from APIntOps namespace. Replace the few ↵Craig Topper2017-03-312-9/+9
| | | | | | users with the APInt class methods. NFCI llvm-svn: 299248
* Do not translate rint into nearbyint, but truncate it like nearbyint.Joerg Sonnenberger2017-03-312-1/+3
| | | | | | | | | | | | | | A common way to implement nearbyint is by fiddling with the floating point environment and calling rint. This is used at least by the BSD libm and musl. As such, canonicalizing the latter to the former will create infinite loops for libm and generally pessimize performance, at least when the generic C versions are used. This change preserves the rint in the libcall translation and also handles the domain truncation logic, so that rint with float argument will be reduced to rintf etc. llvm-svn: 299247
* AMDGPU: Remove unnecessary ands when f16 is legalMatt Arsenault2017-03-316-2/+57
| | | | | | | | | | Add a new node to act as a fancy bitcast from f16 operations to i32 that implicitly zero the high 16-bits of the result. Alternatively could try making v2f16 legal and canonicalizing on build_vectors. llvm-svn: 299246
* AMDGPU/R600: Fix amdgpu alias analysis pass.Jan Vesely2017-03-312-5/+11
| | | | | | | | | R600 uses higher AS number to access kernel parameters Fixes: r298846 Differential Revision: https://reviews.llvm.org/D31520 llvm-svn: 299245
* [APInt] Rewrite getLoBits in a way that will do one less memory allocation ↵Craig Topper2017-03-311-3/+4
| | | | | | in the multiword case. Rewrite getHiBits to use the class method version of lshr instead of the one in APIntOps. NFCI llvm-svn: 299243
* [DAGCombiner] remove redundant code and add comments; NFCISanjay Patel2017-03-311-10/+13
| | | | llvm-svn: 299241
* [AArch64] Add new subtarget feature to fold LSL into address mode.Balaram Makam2017-03-313-5/+53
| | | | | | | | | | | | | Summary: This feature enables folding of logical shift operations of up to 3 places into addressing mode on Kryo and Falkor that have a fastpath LSL. Reviewers: mcrosier, rengolin, t.p.northover Subscribers: junbuml, gberry, llvm-commits, aemerson Differential Revision: https://reviews.llvm.org/D31113 llvm-svn: 299240
* [AVX-512] Update lowering for gather/scatter prefetch intrinsics to match ↵Craig Topper2017-03-311-3/+3
| | | | | | | | | | the immediate encodings the frontend uses based on the _MM_HINT_T0/T1 constant values in clang's headers. Our _MM_HINT_T0/T1 constant values are 3/2 which matches gcc, but not icc or Intel documentation. Interestingly gcc had this same bug on their implementation of the gather/scatter builtins at one point too. Fixes PR32411. llvm-svn: 299234
* Fix the InstCombine to reserve the VP metadata and sets correct call count.Dehao Chen2017-03-312-8/+23
| | | | | | | | | | | | | | Summary: Currently the VP metadata was dropped when InstCombine converts a call to direct call. This patch converts the VP metadata to branch_weights so that its hotness is recorded. Reviewers: eraman, davidxl Reviewed By: davidxl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31344 llvm-svn: 299228
* Refactor code to create getFallThrough method in MachineBasicBlock.Jan Sjodin2017-03-311-8/+14
| | | | | | Differential Revision: https://reviews.llvm.org/D27264 llvm-svn: 299227
* Remove name space pollution from Signals.cppKristof Beyls2017-03-313-5/+4
| | | | llvm-svn: 299224
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