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* Use IRBuilder while simplifying switch instruction.Devang Patel2011-05-181-15/+18
| | | | llvm-svn: 131566
* Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' ↵Johnny Chen2011-05-181-1/+1
| | | | | | immediate operand. llvm-svn: 131565
* Use IRBuilder while simplifying unwind.Devang Patel2011-05-181-7/+9
| | | | llvm-svn: 131561
* Enables vararg functions that pass all arguments via registers to be ↵Chad Rosier2011-05-181-5/+18
| | | | | | optimized into tail-calls when possible. llvm-svn: 131560
* More instcombine cleanup aimed towards improving debug line info.Eli Friedman2011-05-181-21/+18
| | | | llvm-svn: 131559
* Second pass at allowing plugins to modify default passes. This time without ↵David Chisnall2011-05-181-0/+247
| | | | | | bonus inter-library dependencies. llvm-svn: 131556
* Revise r131553. Just use the type of the input node and forgo the bitcast. ↵Evan Cheng2011-05-181-4/+3
| | | | | | rdar://9449159. llvm-svn: 131555
* Fix an ARMTargetLowering::LowerSELECT bug: legalized result must have same ↵Evan Cheng2011-05-181-1/+3
| | | | | | type as input. Sorry test cases only trigger when dag combine is disabled. rdar://9449178 llvm-svn: 131553
* Use IRBuilder while simplifying terminator.Devang Patel2011-05-181-4/+7
| | | | llvm-svn: 131552
* Use IRBuilder while simplifying unconditional branch.Devang Patel2011-05-181-6/+11
| | | | llvm-svn: 131551
* Use IRBuilder while folding two entry PHINode.Devang Patel2011-05-181-6/+8
| | | | llvm-svn: 131548
* Switch more inst insertion in instcombine to IRBuilder.Eli Friedman2011-05-181-10/+6
| | | | llvm-svn: 131547
* Set up IRBuilder for use during simplification.Devang Patel2011-05-181-0/+3
| | | | llvm-svn: 131545
* Switch more inst insertion in instcombine to IRBuilder.Eli Friedman2011-05-181-13/+6
| | | | llvm-svn: 131544
* fix typoMatt Beaumont-Gay2011-05-181-1/+1
| | | | llvm-svn: 131543
* Switch inst insertion in instcombine transform to IRBuilder.Eli Friedman2011-05-181-6/+2
| | | | llvm-svn: 131542
* Use IRBuiler while constant folding terminator.Devang Patel2011-05-182-9/+12
| | | | llvm-svn: 131541
* Fix inelegant initialization.Stuart Hastings2011-05-181-2/+1
| | | | llvm-svn: 131538
* PTX: add flag to disable mad/fma selectionJustin Holewinski2011-05-184-4/+19
| | | | | | Patch by Dan Bailey llvm-svn: 131537
* Revert commit 131534 since it seems to have broken several buildbots.Duncan Sands2011-05-184-6/+6
| | | | | | | | Original log entry: Refactor getActionType and getTypeToTransformTo ; place all of the 'decision' code in one place. llvm-svn: 131536
* Refactor getActionType and getTypeToTransformTo ; place all of the 'decision'Nadav Rotem2011-05-184-6/+6
| | | | | | code in one place. llvm-svn: 131534
* Now that SrcBits and DestBits always represent the primitive size, ratherDuncan Sands2011-05-181-55/+29
| | | | | | | | | than either the primitive size or the element primitive size (in the case of vectors), simplify the vector logic. No functionality change. There is some distracting churn in the patch because I lined up comments better while there - sorry about that. llvm-svn: 131533
* Tighten up checking of the validity of casts. (1) The IR parser wouldDuncan Sands2011-05-181-32/+28
| | | | | | | | | | | | | | happily accept things like "sext <2 x i32> to <999 x i64>". It would also accept "sext <2 x i32> to i64", though the verifier would catch that later. Fixed by having castIsValid check that vector lengths match except when doing a bitcast. (2) When creating a cast instruction, check that the cast is valid (this was already done when creating constexpr casts). While there, replace getScalarSizeInBits (used to allow more vector casts) with getPrimitiveSizeInBits in getCastOpcode and isCastable since vector to vector casts are now handled explicitly by passing to the element types; i.e. this bit should result in no functional change. llvm-svn: 131532
* Teach getCastOpcode about element-by-element vector casts. For example, "trunc"Duncan Sands2011-05-181-4/+25
| | | | | | | | | | | | | can be used to turn a <4 x i64> into a <4 x i32> but getCastOpcode would assert if you passed these types to it. Note that this strictly extends the previous functionality: if getCastOpcode previously accepted two vector types (i.e. didn't assert) then it still will and returns the same opcode (BitCast). That's because before it would only accept vectors with the same bitwidth, and the new code only touches vectors with the same length. However if two vectors have both the same bitwidth and the same length then their element types have the same bitwidth, so the new logic will return BitCast as before. llvm-svn: 131530
* In r131488 I misunderstood how VREV works. It splits the vector in half and ↵Tanya Lattner2011-05-182-1343/+1350
| | | | | | | | splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32. Updated test case and reverted change to the PerfectShuffle Table. llvm-svn: 131529
* Implement the Win64 EH directive methods for the assembly language streamer.Charles Davis2011-05-181-0/+77
| | | | | | | | | GAS has no such directives (not even mingw-w64 GAS has them), so I took creative license with their names in assembly. I prefixed them all with "w64_" to avoid namespace collisions, for example. If I discover that GAS has taken a different approach, I'll change ours to match. llvm-svn: 131525
* Eliminate dead dead code elimination code.Jakob Stoklund Olesen2011-05-182-292/+0
| | | | llvm-svn: 131524
* Also use shrinkToUses after AdjustCopiesBackFrom().Jakob Stoklund Olesen2011-05-181-1/+1
| | | | | | | The 'last use' may not be in the same basic block, and we still want a correct live range. llvm-svn: 131523
* While thinking about how to know where the functions' boundaries are forCharles Davis2011-05-181-2/+8
| | | | | | | | | the purposes of the Win64 EH tables, I realized we had no way to tell where the function ends. (MASM bounds functions with PROC and ENDP keywords.) Add a directive to delimit the end of the function, and rename the 'frame' directive to more accurately reflect its duality with the new directive. llvm-svn: 131522
* Properly shrink live ranges after deleting dead copies. Clean up after all ↵Jakob Stoklund Olesen2011-05-181-24/+5
| | | | | | | | | | | | | joined copies. LiveInterval::shrinkToUses recomputes the live range from scratch instead of removing snippets. This should avoid the problem with dangling live ranges. Leave physreg identity copies alone. They can be created when joining a virtreg with a physreg. They don't affect register allocation, and they will be removed by the rewriter. llvm-svn: 131521
* Fix typo.Cameron Zwarich2011-05-181-4/+4
| | | | llvm-svn: 131519
* Fix more of PR8825 by correctly using rGPR registers when lowering atomicCameron Zwarich2011-05-181-2/+11
| | | | | | compare-and-swap intrinsics. llvm-svn: 131518
* Start trying to make InstCombine preserve more debug info. The idea here is ↵Eli Friedman2011-05-182-5/+6
| | | | | | | | | | to set the debug location on the IRBuilder, which will be then right location in most cases. This should magically give many transformations debug locations, and fixing places which are missing a debug location will usually just means changing the code creating it to use the IRBuilder. As an example, the change to InstCombineCalls catches a common case where a call to a bitcast of a function is rewritten. Chris, does this approach look reasonable? llvm-svn: 131516
* Use ReplaceInstUsesWith instead of replaceAllUsesWith where appropriate in ↵Eli Friedman2011-05-183-11/+11
| | | | | | instcombine. llvm-svn: 131512
* Preseve line numbers while simplifying CFG.Devang Patel2011-05-171-6/+16
| | | | llvm-svn: 131508
* Actually, the address operand of the Thumb2 LDREX / STREX instructions *can*Cameron Zwarich2011-05-171-1/+1
| | | | | | take r13, so we can just make it a GPR. This fixes PR8825. llvm-svn: 131507
* Correct a minor problem with the Thumb2 LDREX and STREX instruction ↵Cameron Zwarich2011-05-171-1/+1
| | | | | | | | encodings. They were marked as taking a tGPR when in reality they take an rGPR. llvm-svn: 131506
* Conditionalize the format of the GCOV files by target type. Darwin uses the 4.2Bill Wendling2011-05-171-10/+19
| | | | | | format. llvm-svn: 131503
* Make fast-isel miss counting in -stats and -fast-isel-verbose take ↵Eli Friedman2011-05-171-3/+8
| | | | | | terminators into account; since there are many fewer isel misses with recent changes, misses caused by terminators are more significant. llvm-svn: 131502
* Misc. code cleanups.Dan Gohman2011-05-171-60/+59
| | | | llvm-svn: 131497
* Misc. code cleanups.Dan Gohman2011-05-171-33/+34
| | | | llvm-svn: 131495
* X86 pmovsx/pmovzx ignore the upper half of their inputs.Stuart Hastings2011-05-172-1/+23
| | | | | | rdar://problem/6945110 llvm-svn: 131493
* vrev is incorrectly defined in the perfect shuffle table. The ordering is ↵Tanya Lattner2011-05-171-6565/+6566
| | | | | | backwards (should be 0x3210 versus 0x1032) which exposed a bug when doing a shuffle on a 4xi16. I've attached a test case. llvm-svn: 131488
* Preserve line number information.Devang Patel2011-05-171-0/+1
| | | | llvm-svn: 131482
* Set debug loc for new load instruction.Devang Patel2011-05-171-0/+3
| | | | llvm-svn: 131481
* Preserve line number information.Devang Patel2011-05-171-1/+2
| | | | llvm-svn: 131480
* Enable autodetect of popcntMon P Wang2011-05-171-0/+1
| | | | llvm-svn: 131476
* Add x86 fast-isel for calls returning first-class aggregates. rdar://9435872.Eli Friedman2011-05-171-46/+51
| | | | | | This is r131438 with a couple small fixes. llvm-svn: 131474
* Clean up the mess created by r131467+r131469.Eli Friedman2011-05-172-16/+0
| | | | llvm-svn: 131471
* Revert 131467 due to buildbot complaint.Stuart Hastings2011-05-173-80/+30
| | | | llvm-svn: 131469
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