summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* R600: Rework subtarget info and remove AMDILDevice classesTom Stellard2013-06-0736-1458/+218
| | | | | | | | This should simplify the subtarget definitions and make it easier to add new ones. Reviewed-by: Vincent Lejeune <vljn@ovi.com> llvm-svn: 183566
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-074-9/+10
| | | | | | | | the internals of TargetMachine could change. No functionality change intended. llvm-svn: 183565
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-0721-63/+75
| | | | | | | | the internals of TargetMachine could change. No functionality change intended. llvm-svn: 183561
* R600: Fix the fetch limits for R600 generation GPUsTom Stellard2013-06-074-27/+30
| | | | | | | | Reviewed-by: Vincent Lejeune <vljn@ovi.com> https://bugs.freedesktop.org/show_bug.cgi?id=64257 llvm-svn: 183560
* R600: Move Subtarget feature definitions into AMDGPU.tdTom Stellard2013-06-072-64/+66
| | | | | | | This is the convention used by the other targets. Reviewed-by: Vincent Lejeune <vljn@ovi.com> llvm-svn: 183559
* R600: Remove unnecessary includeTom Stellard2013-06-073-2/+4
| | | | | Reviewed-by: Vincent Lejeune <vljn@ovi.com> llvm-svn: 183558
* Add a backend option to warn on a given stack size limit.Quentin Colombet2013-06-071-0/+13
| | | | | | | | | | | | Option: -mllvm -warn-stack-size=<limit> Output (if limit is exceeded): warning: Stack size limit exceeded (<actual size>) in <functionName>. The longer term plan is to hook that to a clang warning. PR:4072 <rdar://problem/13987214> llvm-svn: 183552
* ARM FastISel integer sext/zext improvementsJF Bastien2013-06-071-38/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | My recent ARM FastISel patch exposed this bug: http://llvm.org/bugs/show_bug.cgi?id=16178 The root cause is that it can't select integer sext/zext pre-ARMv6 and asserts out. The current integer sext/zext code doesn't handle other cases gracefully either, so this patch makes it handle all sext and zext from i1/i8/i16 to i8/i16/i32, with and without ARMv6, both in Thumb and ARM mode. This should fix the bug as well as make FastISel faster because it bails to SelectionDAG less often. See fastisel-ext.patch for this. fastisel-ext-tests.patch changes current tests to always use reg-imm AND for 8-bit zext instead of UXTB. This simplifies code since it is supported on ARMv4t and later, and at least on A15 both should perform exactly the same (both have exec 1 uop 1, type I). 2013-05-31-char-shift-crash.ll is a bitcode version of the above bug 16178 repro. fast-isel-ext.ll tests all sext/zext combinations that ARM FastISel should now handle. Note that my ARM FastISel enabling patch was reverted due to a separate failure when dealing with MCJIT, I'll fix this second failure and then turn FastISel on again for non-iOS ARM targets. I've tested "make check-all" on my x86 box, and "lnt test-suite" on A15 hardware. llvm-svn: 183551
* R600: Don't compare iterators of different maps.Benjamin Kramer2013-06-071-1/+1
| | | | | | Found be libstdc's debug mode. llvm-svn: 183549
* Teach AsmPrinter how to print odd constants.Quentin Colombet2013-06-071-2/+43
| | | | | | | | | | | Fix an assertion when the compiler encounters big constants whose bit width is not a multiple of 64-bits. Although clang would never generate something like this, the backend should be able to handle any legal IR. <rdar://problem/13363576> llvm-svn: 183544
* DIBuilder: No functionality change.Manman Ren2013-06-071-23/+26
| | | | | | Use the correct DIType when creating types in DIBuilder. llvm-svn: 183543
* Vincent says the element is at most once in the vector, so we don't need a ↵Benjamin Kramer2013-06-071-3/+7
| | | | | | full std::remove. llvm-svn: 183541
* Use isxdigit.Rafael Espindola2013-06-071-9/+1
| | | | | | Thanks to Benjamin Kramer for the suggestion. llvm-svn: 183540
* Fix a typo in asm string of BP* family of instructions. With this fixRoman Divacky2013-06-071-1/+1
| | | | | | I am able to compile/assemble/link/run /bin/echo from FreeBSD. llvm-svn: 183537
* Support OpenBSD's native frame protection conventions.Rafael Espindola2013-06-071-11/+36
| | | | | | | | | | | | | | | OpenBSD's stack smashing protection differs slightly from other platforms: 1. The smash handler function is "__stack_smash_handler(const char *funcname)" instead of "__stack_chk_fail(void)". 2. There's a hidden "long __guard_local" object that gets linked into each executable and DSO. Patch by Matthew Dempsky. llvm-svn: 183533
* R600: Fix a potential iterator invalidation issue.Benjamin Kramer2013-06-071-5/+3
| | | | | | As a bonus this reduces the loop from O(n^2) to O(n). llvm-svn: 183532
* R600: Remove an extra break in R600OptimizeVectorRegisters.cppVincent Lejeune2013-06-071-3/+1
| | | | llvm-svn: 183528
* Fold variable that's only used in assert into the assert.Benjamin Kramer2013-06-071-2/+1
| | | | | | Avoids unused variable warnings in Release builds. llvm-svn: 183512
* Correct wrong register in this example, pointed out by Baoshan Pang.Duncan Sands2013-06-071-1/+1
| | | | llvm-svn: 183495
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-077-20/+27
| | | | | | | | the internals of TargetMachine could change. No functionality change intended. llvm-svn: 183494
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-0711-40/+67
| | | | | | the internals of TargetMachine could change. llvm-svn: 183493
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-073-6/+5
| | | | | | the internals of TargetMachine could change. llvm-svn: 183492
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-074-10/+6
| | | | | | the internals of TargetMachine could change. llvm-svn: 183491
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-079-19/+25
| | | | | | the internals of TargetMachine could change. llvm-svn: 183490
* [objc-arc] Ensure that the cfg path count does not overflow when we multiply ↵Michael Gottesman2013-06-071-10/+38
| | | | | | | | TopDownPathCount/BottomUpPathCount. rdar://12480535 llvm-svn: 183489
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-0715-42/+48
| | | | | | the internals of TargetMachine could change. llvm-svn: 183488
* Don't cache the instruction info and register info objects.Bill Wendling2013-06-076-28/+22
| | | | | | These objects are internal to the TargetMachine object and may change. llvm-svn: 183485
* DIBuilder: No functionality change.Manman Ren2013-06-071-3/+3
| | | | | | Use the correct DIType when creating vector types. llvm-svn: 183484
* ARM sched model: Use the right resources for DIVArnold Schwaighofer2013-06-071-1/+1
| | | | llvm-svn: 183477
* ARM sched model: Add VFP div instruction on SwiftArnold Schwaighofer2013-06-071-0/+16
| | | | | | Reapply 183271. llvm-svn: 183472
* ARM sched model: Add SIMD/VFP load/store instructions on SwiftArnold Schwaighofer2013-06-071-0/+364
| | | | | | | | Reapply 183270 again (because three is a magic number). This should now no longer seg fault after r183459. llvm-svn: 183464
* [Sparc]: Use cmp instruction instead of subcc to compare integers.Venkatraman Govindaraju2013-06-073-17/+19
| | | | llvm-svn: 183463
* Simplify code. No functionality change.Jakub Staszak2013-06-061-2/+1
| | | | llvm-svn: 183461
* R600: Rewrite an awkward loop in R600MachineSchedulerVincent Lejeune2013-06-061-7/+15
| | | | llvm-svn: 183458
* Jeffrey Yasskin volunteered to benchmark the vectorizer on -O2 or -Os when ↵Nadav Rotem2013-06-061-1/+7
| | | | | | compiling chrome. This patch adds a new flag to enable vectorization on all levels and not only on -O3. It should go away once we make a decision. llvm-svn: 183456
* Fix break in r183446 - helps to increment the iterator in a loopDavid Blaikie2013-06-061-1/+2
| | | | llvm-svn: 183454
* Revert "ARM sched model: Add SIMD/VFP load/store instructions on Swift"Arnold Schwaighofer2013-06-061-364/+0
| | | | | | Breaks linux build bots (I thought the problem was something else). llvm-svn: 183447
* Debug Info: simplify parameter ordering preservationDavid Blaikie2013-06-061-25/+21
| | | | | | | | | | | | | Seems we emit the parameter ordering number (spuriously named 'arg number') in the debug info, so there's no need to search through the variable list to figure out the parameter ordering. This implementation does 'always' do the work, even in non-optimized debug info (the previous implementation checked the existence of the 'variables' list on the subprogram which is only present in optimized builds). No intended functionality change. llvm-svn: 183446
* ARM sched model: Add SIMD/VFP load/store instructions on SwiftArnold Schwaighofer2013-06-061-0/+364
| | | | | | Reapply 183270. llvm-svn: 183445
* ARM sched model: Add integer VFP/SIMD instructions on SwiftArnold Schwaighofer2013-06-063-0/+125
| | | | | | Reapply 183269. llvm-svn: 183441
* Re-apply "Use IRBuilder instead of ConstantInt methods." with the fixed issues.Jakub Staszak2013-06-061-68/+55
| | | | llvm-svn: 183439
* ARM sched model: Add integer load/store instructions on SwiftArnold Schwaighofer2013-06-061-0/+209
| | | | | | Reapply 183268. llvm-svn: 183438
* ARM sched model: Add integer arithmetic instructions on SwiftArnold Schwaighofer2013-06-061-0/+155
| | | | | | Reapply 183267. llvm-svn: 183436
* ARM sched model: Cortex A9 - More InstRW sched resourcesArnold Schwaighofer2013-06-061-4/+45
| | | | | | | | Add more InstRW mappings. Reapply 183266. llvm-svn: 183435
* ARM sched model: Add branch thumb instructionsArnold Schwaighofer2013-06-061-18/+21
| | | | | | Reapply 183265. llvm-svn: 183432
* ARM sched model: Add branch thumb2 instructionsArnold Schwaighofer2013-06-061-11/+15
| | | | | | Reapply 183264. llvm-svn: 183430
* ARM sched model: Add branch instructionsArnold Schwaighofer2013-06-061-27/+35
| | | | | | Reapply 183263. llvm-svn: 183428
* ARM sched model: Add preload thumb2 instructionsArnold Schwaighofer2013-06-061-3/+6
| | | | | | Reapply 183262. llvm-svn: 183427
* ARM sched model: Add preload instructionsArnold Schwaighofer2013-06-061-2/+4
| | | | | | Reapply 183261. llvm-svn: 183425
* Teach llvm-objdump with the -macho parser how to use the data in code tableKevin Enderby2013-06-061-1/+45
| | | | | | | | | | | | | | | from the LC_DATA_IN_CODE load command. And when disassembling print the data in code formatted for the kind of data it and not disassemble those bytes. I added the format specific functionality to the derived class MachOObjectFile since these tables only appears in Mach-O object files. This is my first attempt to modify the libObject stuff so if folks have better suggestions how to fit this in or suggestions on the implementation please let me know. rdar://11791371 llvm-svn: 183424
OpenPOWER on IntegriCloud