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* AArch64: enable Cortex-A57 FP balancing on Cortex-A53.Tim Northover2014-10-281-1/+2
| | | | | | | | | | Benchmarks have shown that it's harmless to the performance there, and having a unified set of passes between the two cores where possible helps big.LITTLE deployment. Patch by Z. Zheng. llvm-svn: 220744
* Remove the PreserveSource linker mode.Rafael Espindola2014-10-281-29/+20
| | | | | | | | | | | | | | | | | | | | I noticed that it was untested, and forcing it on caused some tests to fail: LLVM :: Linker/metadata-a.ll LLVM :: Linker/prefixdata.ll LLVM :: Linker/type-unique-odr-a.ll LLVM :: Linker/type-unique-simple-a.ll LLVM :: Linker/type-unique-simple2-a.ll LLVM :: Linker/type-unique-simple2.ll LLVM :: Linker/type-unique-type-array-a.ll LLVM :: Linker/unnamed-addr1-a.ll LLVM :: Linker/visibility1.ll If it is to be resurrected, it has to be fixed and we should probably have a -preserve-source command line option in llvm-mc and run tests with and without it. llvm-svn: 220741
* AArch64InstrInfo.h: Fix a warning introduced in clang r220703. ↵NAKAMURA Takumi2014-10-271-1/+1
| | | | | | [-Winconsistent-missing-override] llvm-svn: 220739
* [AVX512] Add vpermil variable versionAdam Nemet2014-10-271-2/+25
| | | | | | | | | This is implemented via a multiclass that derives from the vperm imm multiclass. Fixes <rdar://problem/18426089> llvm-svn: 220737
* [AVX512] Clean up avx512_perm_imm to use X86VectorVTInfoAdam Nemet2014-10-271-25/+22
| | | | | | | | No functionality change. No change in X86.td.expanded except that we only set the CD8 attributes for the memory variants. (This shouldn't be used unless we have a memory operand.) llvm-svn: 220736
* [AVX512] Derive vpermil* from avx512_perm_immAdam Nemet2014-10-271-14/+14
| | | | | | | | This used to derive from avx512_pshuf_imm which is confusing. NFC. Compared X86.td.expanded. llvm-svn: 220735
* [AVX512] Fix copy-and-paste bugs in vpermilAdam Nemet2014-10-271-3/+3
| | | | | | | | | 1) i512mem -> f512mem (this is the packed FP input being permuted) 2) element size is 64 bits in EVEX_CD8 for PD. (A good illustration why X86VectorVTInfo is useful) llvm-svn: 220734
* Make it easier to pass a custom diagnostic handler to the IR linker.Rafael Espindola2014-10-271-27/+27
| | | | llvm-svn: 220732
* Fix a stackmap bug introduced in r220710.Pete Cooper2014-10-271-4/+14
| | | | | | | | For a call to not return in to the stackmap shadow, the shadow must end with the call. To do this, we must insert any required nops *before* the call, and not after it. llvm-svn: 220728
* Fix bug where sys::Wait could wait on wrong pid.Rafael Espindola2014-10-271-1/+0
| | | | | | | | Setting ChildPid to -1 would cause waitpid to wait for any child process. Patch by Daniel Reynaud! llvm-svn: 220717
* [FastISel][AArch64] Emit immediate version of icmp (subs) for null pointer ↵Juergen Ributzka2014-10-271-2/+6
| | | | | | | | | | | | check. This is a minor change to use the immediate version when the operand is a null value. This should get rid of an unnecessary 'mov' instruction in debug builds and align the code more with the one generated by SelectionDAG. This fixes rdar://problem/18785125. llvm-svn: 220713
* [FastISel][AArch64] Optimize compare-and-branch for i1 to use 'tbz'.Juergen Ributzka2014-10-271-0/+4
| | | | | | | | | Minor enhancement to use 'tbz' for i1 compare-and-branch to get rid of an 'and' instruction. This fixes rdar://problem/18784953. llvm-svn: 220712
* Stackmap shadows should consider call returns a branch target.Pete Cooper2014-10-271-0/+6
| | | | | | | | To avoid emitting too many nops, a stackmap shadow can include emitted instructions in the shadow, but these must not include branch targets. A return from a call should count as a branch target as patching over the instructions after the call would lead to incorrect behaviour for threads currently making that call, when they return. llvm-svn: 220710
* [FastISel][AArch64] Use 'cbz' also for null values (pointers).Juergen Ributzka2014-10-271-15/+12
| | | | | | | | | The pattern matching for a 'ConstantInt' value was too restrictive. Checking for a 'Constant' with a bull value is sufficient for using an 'cbz/cbnz' instruction. This fixes rdar://problem/18784732. llvm-svn: 220709
* [FastISel][AArch64] Don't fold the 'and' instruction into the 'tbz/tbnz' ↵Juergen Ributzka2014-10-271-2/+2
| | | | | | | | | | | | instruction if it is in a different basic block. This fixes a bug where the input register was not defined for the 'tbz/tbnz' instruction. This happened, because we folded the 'and' instruction from a different basic block. This fixes rdar://problem/18784013. llvm-svn: 220704
* [FastISel][AArch64] Fix load/store with frame indices.Juergen Ributzka2014-10-271-23/+20
| | | | | | | | | | | | At higher optimization levels the LLVM IR may contain more complex patterns for loads/stores from/to frame indices. The 'computeAddress' function wasn't able to handle this and triggered an assertion. This fix extends the possible addressing modes for frame indices. This fixes rdar://problem/18783298. llvm-svn: 220700
* [asan] experimental tracing for indirect calls, llvm part.Kostya Serebryany2014-10-271-4/+44
| | | | llvm-svn: 220699
* [PBQP] Unique allowed-sets for nodes in the PBQP graph and use pairs of theseLang Hames2014-10-272-37/+58
| | | | | | | | | | | sets as keys into a cache of interference matrice values in the Interference constraint adder. Creating interference matrices was one of the large remaining time-sinks in PBQP. Caching them reduces the total compile time (when using PBQP) on the nightly test suite by ~10%. llvm-svn: 220688
* Prune CRLF.NAKAMURA Takumi2014-10-272-138/+138
| | | | llvm-svn: 220678
* [ARM] Select VMAXNM and VMINNM regardless of operand orderOliver Stannard2014-10-271-6/+12
| | | | | | | | | | | | | | Currently, the ARM backend will select the VMAXNM and VMINNM for these C expressions: (a < b) ? a : b (a > b) ? a : b but not these expressions: (a > b) ? b : a (a < b) ? b : a This patch allows all of these expressions to be matched. llvm-svn: 220671
* [asan-asm-instrumentation] Added comment describing how asm instrumentation ↵Yuri Gorshenin2014-10-271-0/+64
| | | | | | | | | | | | | | works. Summary: [asan-asm-instrumentation] Added comment describing how asm instrumentation works. Reviewers: eugenis Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5970 llvm-svn: 220670
* Fix unicode chars into ascii in comment lines.NAKAMURA Takumi2014-10-271-1/+1
| | | | llvm-svn: 220668
* InstCombine: Fix a combine assuming that icmp operands were integersDavid Majnemer2014-10-271-0/+4
| | | | | | | | | An icmp may have pointer arguments, it isn't limited to integers or vectors of integers. This fixes PR21388. llvm-svn: 220664
* LinkModules.cpp: don't repeat names in comments.Rafael Espindola2014-10-271-69/+61
| | | | llvm-svn: 220662
* Remove some unnecessary casts.David Blaikie2014-10-261-2/+2
| | | | llvm-svn: 220658
* Add an option to the LTO code generator to disable vectorization during LTOArnold Schwaighofer2014-10-262-4/+10
| | | | | | | | | | | | | | | | | | | | We used to always vectorize (slp and loop vectorize) in the LTO pass pipeline. r220345 changed it so that we used the PassManager's fields 'LoopVectorize' and 'SLPVectorize' out of the desire to be able to disable vectorization using the cl::opt flags 'vectorize-loops'/'slp-vectorize' which the before mentioned fields default to. Unfortunately, this turns off vectorization because those fields default to false. This commit adds flags to the LTO library to disable lto vectorization which reconciles the desire to optionally disable vectorization during LTO and the desired behavior of defaulting to enabled vectorization. We really want tools to set PassManager flags directly to enable/disable vectorization and not go the route via cl::opt flags *in* PassManagerBuilder.cpp. llvm-svn: 220652
* AVX-512: Fixed encoding of VPBROADCASTM and added SKX forms of this instructionElena Demikhovsky2014-10-261-8/+17
| | | | llvm-svn: 220638
* LSR: Minor cleanup after Daniel's patch.Andrew Trick2014-10-251-4/+2
| | | | | | Combine the Inserted an Done sets into a Visited set. llvm-svn: 220623
* Fix LSR compile time.Andrew Trick2014-10-251-0/+5
| | | | | | | | | | | | This is a simple fix that brings the compilation time from 5min to 5s on a specific real-world example. It's a large chain of computation in a crypto routine (always a problem for SCEV). A unit test is not feasible and there would be no way to check it. The fix is just basic good practice for dealing with SCEVs, there's no risk of regression. Patch by Daniel Reynaud! llvm-svn: 220622
* [SeparateConstOffsetFromGEP] Fixed a bug related to unsigned moduloJingyue Wu2014-10-251-6/+6
| | | | | | | | | | | The dividend in "signed % unsigned" is treated as unsigned instead of signed, causing unexpected behavior such as -64 % (uint64_t)24 == 0. Added a regression test in split-gep.ll Patched by Hao Liu. llvm-svn: 220618
* Clean up assume intrinsic pattern matching, no need to check that the ↵Benjamin Kramer2014-10-252-12/+7
| | | | | | | | argument is a value. Also make it const safe and remove superfluous casting. NFC. llvm-svn: 220616
* [SeparateConstOffsetFromGEP] Fixed a bug in rebuilding OR expressionsJingyue Wu2014-10-251-2/+7
| | | | | | | | | | | | The two operands of the new OR expression should be NextInChain and TheOther instead of the two original operands. Added a regression test in split-gep.ll. Hao Liu reported this bug, and provded the test case and an initial patch. Thanks! llvm-svn: 220615
* [X86][SSE] Vector integer/float conversion memory foldingSimon Pilgrim2014-10-251-7/+7
| | | | | | | | Tidied up some entries in the folding tables so that they are under the correct comment section (they were categorised as AVX2 instructions when they're AVX1). Minor patch agreed with qcolombet. llvm-svn: 220613
* InstCombine: Remove overzealous assertsDavid Majnemer2014-10-251-12/+19
| | | | | | | | | | | | | | These asserts can trigger if the worklist iteration order is sufficiently unlucky. Instead of adding special case logic to handle these edge conditions, just bail out on trying to transform them: InstSimplify will get them when it reaches them on the worklist. This fixes PR21378. N.B. No test case is included because any test would rely on the fragile worklist iteration order. llvm-svn: 220612
* Allow the C API users to keep relying on the OutMessages parameter.Rafael Espindola2014-10-251-1/+26
| | | | | | Should fix the Ocaml tests. llvm-svn: 220611
* Update the error handling of lib/Linker.Rafael Espindola2014-10-252-75/+81
| | | | | | Instead of passing a std::string&, use the new diagnostic infrastructure. llvm-svn: 220608
* [NVPTX] aligned byte-buffers for vector return typesJingyue Wu2014-10-251-1/+6
| | | | | | | | | | | | | | | | | | | Summary: Fixes PR21100 which is caused by inconsistency between the declared return type and the expected return type at the call site. The new behavior is consistent with nvcc and the NVPTXTargetLowering::getPrototype function. Test Plan: test/Codegen/NVPTX/vector-return.ll Reviewers: jholewinski Reviewed By: jholewinski Subscribers: llvm-commits, meheff, eliben, jholewinski Differential Revision: http://reviews.llvm.org/D5612 llvm-svn: 220607
* [msan] Make -msan-check-constant-shadow a bit stronger.Evgeniy Stepanov2014-10-241-3/+10
| | | | | | Allow (under the experimental flag) non-Instructions to participate in MSan checks. llvm-svn: 220601
* Modernize the error handling of the Materialize function.Rafael Espindola2014-10-246-20/+18
| | | | llvm-svn: 220600
* Fix a Mach-O assembler segfault for a subtraction expression with an ↵Kevin Enderby2014-10-241-4/+7
| | | | | | | | | | | | | | | | | undefined symbol. In a Mach-O object file a relocatable expression of the form SymbolA - SymbolB + constant is allowed when both symbols are defined in a section. But when either symbol is undefined it is an error. The code was crashing when it had an undefined symbol in this case. And should have printed a error message using the location information in the relocation entry. rdar://18678402 llvm-svn: 220599
* Sink DwarfUnit::constructImportedEntityDIE into DwarfCompileUnit.Frederic Riss2014-10-244-32/+32
| | | | | | | | | | So that it has access to getOrCreateGlobalVariableDIE. If we ever support decsribing using directive in C++ classes (thus requiring support in type units), it will certainly use another mechanism anyway. Differential Revision: http://reviews.llvm.org/D5975 llvm-svn: 220594
* [X86][SSE] Bitcast assertion in XFormVExtractWithShuffleIntoLoadSimon Pilgrim2014-10-241-9/+12
| | | | | | | | | | Minor patch to fix an issue in XFormVExtractWithShuffleIntoLoad where a load is unary shuffled, then bitcast (to a type with the same number of elements) before extracting an element. An undef was created for the second shuffle operand using the original (post-bitcasted) vector type instead of the pre-bitcasted type like the rest of the shuffle node - this was then causing an assertion on the different types later on inside SelectionDAG::getVectorShuffle. Differential Revision: http://reviews.llvm.org/D5917 llvm-svn: 220592
* [Hexagon] Resubmission of 220427Colin LeMahieu2014-10-2419-233/+241
| | | | | | | | | | | Modified library structure to deal with circular dependency between HexagonInstPrinter and HexagonMCInst. Adding encoding bits for add opcode. Adding llvm-mc tests. Removing unit tests. http://reviews.llvm.org/D5624 llvm-svn: 220584
* Fix copy paste commentMatt Arsenault2014-10-241-2/+2
| | | | llvm-svn: 220581
* Don't ever call materializeAllPermanently during LTO.Rafael Espindola2014-10-248-51/+47
| | | | | | | | | | To do this, change the representation of lazy loaded functions. The previous representation cannot differentiate between a function whose body has been removed and one whose body hasn't been read from the .bc file. That means that in order to drop a function, the entire body had to be read. llvm-svn: 220580
* Allow AVX vrsqrtps generation.Sanjay Patel2014-10-241-2/+3
| | | | | | | This is a follow-on to r220570 that allows a 256-bit (v8f32) version of vrsqrtps to be generated. llvm-svn: 220579
* DebugInfo: Sink DwarfDebug::ScopeVariables down into DwarfFileDavid Blaikie2014-10-245-11/+11
| | | | | | | | (part of refactoring to allow subprogram emission in both the skeleton and main units to enable -gmlt-like data to be included in the skeleton for live inlined backtracing purposes) llvm-svn: 220578
* Remove DwarfDebug::FirstCU as it has no useDavid Blaikie2014-10-242-17/+5
| | | | | | | It was only being used as a flag to identify the lack of debug info from within endModule - use the section labels for that instead. llvm-svn: 220575
* Use rsqrt (X86) to speed up reciprocal square root calcsSanjay Patel2014-10-248-43/+128
| | | | | | | | | | | | | | | | | | | | | This is a first step for generating SSE rsqrt instructions for reciprocal square root calcs when fast-math is allowed. For now, be conservative and only enable this for AMD btver2 where performance improves significantly - for example, 29% on llvm/projects/test-suite/SingleSource/Benchmarks/BenchmarkGame/n-body.c (if we convert the data type to single-precision float). This patch adds a two constant version of the Newton-Raphson refinement algorithm to DAGCombiner that can be selected by any target via a parameter returned by getRsqrtEstimate().. See PR20900 for more details: http://llvm.org/bugs/show_bug.cgi?id=20900 Differential Revision: http://reviews.llvm.org/D5658 llvm-svn: 220570
* [mips] Replace MipsABIEnum with a MipsABIInfo class.Daniel Sanders2014-10-247-32/+70
| | | | | | | | | | | | | | | | | | | | | Summary: No functional change yet, it's just an object replacement for an enum. It will allow us to gather ABI information in a single place so that we can start testing for properties of the ABI's instead of the ABI itself. For example we will eventually be able to use: ABI.MinStackAlignmentInBytes() instead of: (isABI_N32() || isABI_N64()) ? 16 : 8 which is clearer and more maintainable. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3341 llvm-svn: 220568
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