summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* Add support for scalarizing cttz_zero_undefPetar Jovanovic2014-08-101-0/+1
| | | | | | | | | Follow up to r214266. Add missing case in ScalarizeVectorResult() for cttz_zero_undef. Differential Revision: http://reviews.llvm.org/D4813 llvm-svn: 215330
* ARM: correct isPredicable for MULS in ThHUMB modeSaleem Abdulrasool2014-08-101-0/+14
| | | | | | | | | | | | | | | | | | The ARM ARM states that CPSR may not be updated by a MUL in thumb mode. Due to an ordering of Thumb 2 Size Reduction and If Conversion, we would end up generating a THUMB MULS inside an IT block. The If Conversion pass uses the TTI isPredicable method to ensure that it can transform a Basic Block. However, because we only check for IT handling on Thumb2 functions, we may miss some cases. Even then, it only validates that the CPSR is not *live* rather than it is not accessed. This corrects the handling for that particular case since the same restriction does not hold on the vast majority of the instructions. This does prevent the IfConversion optimization from kicking in in certain cases, but generating correct code is more valuable. Addresses PR20555. llvm-svn: 215328
* @l and friends adjust their value depending the context used in.Joerg Sonnenberger2014-08-104-36/+142
| | | | | | | For ori, they are unsigned, for addi, signed. Create a new target expression type to handle this and evaluate Fixups accordingly. llvm-svn: 215315
* Fix tabs.Joerg Sonnenberger2014-08-101-4/+4
| | | | llvm-svn: 215311
* If available, pass down the Fixup object to EvaluateAsRelocatable.Joerg Sonnenberger2014-08-1015-46/+61
| | | | | | | At least on PowerPC, the interpretation of certain modifiers depends on the context they appear in. llvm-svn: 215310
* ADT: remove MinGW32 and Cygwin OSType enumSaleem Abdulrasool2014-08-091-9/+13
| | | | | | | | | | | Remove the MinGW32 and Cygwin types from the OSType enumeration. These values are represented via environments of Windows. It is a source of confusion and needlessly clutters the code. The cost of doing this is that we must sink the check for them into the normalization code path along with the spelling. Addresses PR20592. llvm-svn: 215303
* fixed typosSanjay Patel2014-08-091-2/+2
| | | | llvm-svn: 215299
* Resolving some type truncation warnings in MSVC (enum to bool in this case). ↵Aaron Ballman2014-08-091-3/+3
| | | | | | No functional changes intended. llvm-svn: 215293
* MC: remove duplicated codeSaleem Abdulrasool2014-08-091-14/+2
| | | | | | | | This removes the duplicate definition of GetXDataSection. This function is available as a static method and is identical to the previous implementation. This just cleans up the unnecessary duplication. llvm-svn: 215289
* MC: cleanup includesSaleem Abdulrasool2014-08-091-1/+0
| | | | | | Cleanup Win64EH header inclusion. NFC. llvm-svn: 215288
* CodeGen: switch to a range based for loopSaleem Abdulrasool2014-08-091-3/+4
| | | | | | Use a range based for loop instead of manual iteration. NFC. llvm-svn: 215287
* Allow the third argument for the subi family to be an expression.Joerg Sonnenberger2014-08-091-8/+27
| | | | llvm-svn: 215286
* Use the full form of dccci and iccci from the early PPC 405 documents,Joerg Sonnenberger2014-08-091-15/+9
| | | | | | | since the operands are actually used on those cores. Provide aliases for the only documented case in the newer Power ISA speec. llvm-svn: 215282
* Initialize PPC DataLayout based on the Triple only.Eric Christopher2014-08-092-11/+12
| | | | llvm-svn: 215281
* Remove extraneous 64-bit argument to the PPC TargetMachine constructorEric Christopher2014-08-094-11/+13
| | | | | | and update initialization. llvm-svn: 215280
* Initialize X86 DataLayout based on the Triple only.Eric Christopher2014-08-092-14/+17
| | | | llvm-svn: 215279
* R600: Disable FP exceptions.Matt Arsenault2014-08-091-0/+5
| | | | llvm-svn: 215277
* Move some X86 subtarget configuration onto the subtarget that's beingEric Christopher2014-08-092-21/+22
| | | | | | created. llvm-svn: 215271
* R600/SI: Custom lower CONCAT_VECTORSTom Stellard2014-08-091-1/+3
| | | | | | | This will lower them using register copies rather than loads and stores to the stack. llvm-svn: 215270
* Fix typo.Eric Christopher2014-08-091-1/+1
| | | | llvm-svn: 215266
* [MCJIT] Simplify immediate decoding code in the RuntimeDyldMachO hierarchy.Lang Hames2014-08-086-44/+49
| | | | | | | | | | | Cleanup only: no functional change. This patch makes RuntimeDyldMachO targets directly responsible for decoding immediates, rather than letting them implement catch a callback from generic code. Since this is a very target specific operation, it makes sense to let the target-specific code drive it. llvm-svn: 215255
* [FastISel][X86] Silence -Wenum-compare warningRui Ueyama2014-08-081-2/+6
| | | | llvm-svn: 215253
* Fix the windows build.Rafael Espindola2014-08-081-1/+1
| | | | | | Sorry for the noise. llvm-svn: 215249
* Reword comment slightly.Eric Christopher2014-08-081-4/+3
| | | | llvm-svn: 215248
* Remove dead code. Fixes pr20544.Rafael Espindola2014-08-082-18/+0
| | | | llvm-svn: 215243
* Convert from Windows to Unix paths in sys::path::native.Rafael Espindola2014-08-081-1/+11
| | | | | | Part of pr20544. Test to follow in a second. llvm-svn: 215241
* Allow large immediates for branch instructions in 32bit mode.Joerg Sonnenberger2014-08-081-3/+17
| | | | llvm-svn: 215240
* Provide an implementation of getNoopForMachoTarget for PPC, otherwiseJoerg Sonnenberger2014-08-082-0/+7
| | | | | | empty functions will assert in the MC object writer. llvm-svn: 215238
* [FastISel][X86] Fix INC/DEC optimization (r215230)Juergen Ributzka2014-08-081-1/+1
| | | | | | | | I accidentally also used INC/DEC for unsigned arithmetic which doesn't work, because INC/DEC don't set the required flag which is used for the overflow check. llvm-svn: 215237
* AArch64: avoid deleting the current iterator in a loop.Tim Northover2014-08-081-3/+4
| | | | | | | | std::map invalidates the iterator to any element that gets deleted, which means we can't increment it correctly afterwards. This was causing Darwin test failures. llvm-svn: 215233
* [FastISel][AArch64] Attach MachineMemOperands to load and store instructions.Juergen Ributzka2014-08-081-17/+29
| | | | llvm-svn: 215231
* [FastISel][X86] Use INC/DEC when possible for {sadd|ssub}.with.overflow ↵Juergen Ributzka2014-08-081-5/+24
| | | | | | | | | | intrinsics. This is a small peephole optimization to emit INC/DEC when possible. Fixes <rdar://problem/17952308>. llvm-svn: 215230
* DebugInfo: Recommit (reverted in r215217, originally committed in r215157) ↵David Blaikie2014-08-081-0/+1
| | | | | | | | | the assertion that no argument variable is overwritten by subsequent argument variables. This turned up a bug in clang where arguments were emitted with duplicate argument numbers (see r215227). llvm-svn: 215228
* AArch64A57FPLoadBalancing.cpp: Define ColorNames in !NDEBUG.NAKAMURA Takumi2014-08-081-0/+2
| | | | llvm-svn: 215226
* Delete dead code. NFC.Rafael Espindola2014-08-082-40/+0
| | | | llvm-svn: 215224
* Added a TLI hook to signal that the target does not have or does not care aboutPedro Artigas2014-08-082-5/+11
| | | | | | | | floating point exceptions, added use of flag to fold potentially exception raising floating point math in selection DAG. No functionality change, as targets have to explicitly ask for this behavior and none does today. llvm-svn: 215222
* Add low-level option for avoiding float stores from va_start untilJoerg Sonnenberger2014-08-081-1/+7
| | | | | | soft-float is properly supported. llvm-svn: 215221
* Add support for SPE load/store from memory.Joerg Sonnenberger2014-08-085-0/+202
| | | | llvm-svn: 215220
* getLoadName is only implemented for ELF, make it ELF only.Rafael Espindola2014-08-082-10/+0
| | | | llvm-svn: 215219
* Use a simpler predicate. NFC.Rafael Espindola2014-08-081-31/+19
| | | | llvm-svn: 215218
* DebugInfo: Remove assertion (added in r215157) that's firing on a blocksDavid Blaikie2014-08-081-1/+0
| | | | | | test in the test-suite while I investigate further. llvm-svn: 215217
* pr20589: Fix duplicated arch flag.Rafael Espindola2014-08-081-1/+1
| | | | llvm-svn: 215216
* pr20588: add missing calls to va_end.Rafael Espindola2014-08-081-2/+7
| | | | llvm-svn: 215212
* [mips] Invert the abicalls feature bit to be noabicalls so that it's ↵Daniel Sanders2014-08-083-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | possible for -mno-abicalls to take effect. Also added the testcase that should have been in r215194. This behaviour has surprised me a few times now. The problem is that the generated MipsSubtarget::ParseSubtargetFeatures() contains code like this: if ((Bits & Mips::FeatureABICalls) != 0) IsABICalls = true; so '-abicalls' means 'leave it at the default' and '+abicalls' means 'set it to true'. In this case, (and the similar -modd-spreg case) I'd like the code to be IsABICalls = (Bits & Mips::FeatureABICalls) != 0; or possibly: if ((Bits & Mips::FeatureABICalls) != 0) IsABICalls = true; else IsABICalls = false; and preferably arrange for 'Bits & Mips::FeatureABICalls' to be true by default (on some triples). llvm-svn: 215211
* Add missing Interpreter intrinsic lowering for sin, cos and ceilJosh Klontz2014-08-081-0/+12
| | | | llvm-svn: 215209
* [AArch64] Fix a type conversion bug for anlyzing compare.Jiangning Liu2014-08-081-4/+13
| | | | | | | | The bug can cause spec2006/483.xalancbmk failure. Patched by David Xu. llvm-svn: 215206
* Fix bug 20125 - clang-format segfaults on bad config.Rafael Espindola2014-08-081-1/+6
| | | | | | | The problem was in unchecked dyn_cast inside of Input::createHNodes. Patch by Roman Kashitsyn! llvm-svn: 215205
* [LoopVectorizer] Enable support for floating-point subtraction reductionsJames Molloy2014-08-081-1/+2
| | | | llvm-svn: 215200
* [AArch64] Add an FP load balancing pass for Cortex-A57James Molloy2014-08-084-0/+700
| | | | | | | | | | | | For best-case performance on Cortex-A57, we should try to use a balanced mix of odd and even D-registers when performing a critical sequence of independent, non-quadword FP/ASIMD floating-point multiply or multiply-accumulate operations. This pass attempts to detect situations where the register allocation may adversely affect this load balancing and to change the registers used so as to better utilize the CPU. Ideally we'd just take each multiply or multiply-accumulate in turn and allocate it alternating even or odd registers. However, multiply-accumulates are most efficiently performed in the same functional unit as their accumulation operand. Therefore this pass tries to find maximal sequences ("Chains") of multiply-accumulates linked via their accumulation operand, and assign them all the same "color" (oddness/evenness). This optimization affects S-register and D-register floating point multiplies and FMADD/FMAs, as well as vector (floating point only) muls and FMADD/FMA. Q register instructions (and 128-bit vector instructions) are not affected. llvm-svn: 215199
* [mips] Initial implementation of -mabicalls/-mno-abicalls.Daniel Sanders2014-08-085-9/+20
| | | | | | | | | | | This patch implements the main rules for -mno-abicalls such as reserving $gp, and emitting the correct .option directive. Patch by Matheus Almeida and Toma Tabacu Differential Revision: http://reviews.llvm.org/D4231 llvm-svn: 215194
OpenPOWER on IntegriCloud