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author | Sanjay Patel <spatel@rotateright.com> | 2014-08-09 22:23:02 +0000 |
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committer | Sanjay Patel <spatel@rotateright.com> | 2014-08-09 22:23:02 +0000 |
commit | b48d1cfa5341f54439635bc6ee6ff8e8c3ee6edc (patch) | |
tree | f814704e05521a66c793925957e63db1aca46fa6 /llvm/lib | |
parent | ec740b3d466518f755df14103355bf4ffa717154 (diff) | |
download | bcm5719-llvm-b48d1cfa5341f54439635bc6ee6ff8e8c3ee6edc.tar.gz bcm5719-llvm-b48d1cfa5341f54439635bc6ee6ff8e8c3ee6edc.zip |
fixed typos
llvm-svn: 215299
Diffstat (limited to 'llvm/lib')
-rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 782ba5f7a78..bd920c8ecef 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -1127,7 +1127,7 @@ void X86TargetLowering::resetOperationActions() { setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom); setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom); - // i8 and i16 vectors are custom , because the source register and source + // i8 and i16 vectors are custom because the source register and source // source memory operand types are not the same width. f32 vectors are // custom since the immediate controlling the insert encodes additional // information. @@ -1141,7 +1141,7 @@ void X86TargetLowering::resetOperationActions() { setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); - // FIXME: these should be Legal but thats only for the case where + // FIXME: these should be Legal, but that's only for the case where // the index is constant. For now custom expand to deal with that. if (Subtarget->is64Bit()) { setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); |