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* Add support for __nvvm_reflect changes in libdevice in CUDA-7.0Artem Belevich2015-03-191-5/+32
| | | | | | | | | | | | | | | | | | Summary: CUDA 7.0's libdevice uses slightly different IR to call __nvvm_reflect and that triggers an assertion in nvvm_reflect optimization pass. This change allows nvvm_reflect pass to deal with both old and new ways to pass an argument to __nvvm_reflect. Test Plan: ninja check-all Reviewers: eliben, echristo Subscribers: jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D8399 llvm-svn: 232732
* Switch lowering: remove unnecessary ConstantInt casts. NFC.Hans Wennborg2015-03-192-34/+29
| | | | llvm-svn: 232729
* [Hexagon] Add support for vector instructionsKrzysztof Parzyszek2015-03-195-40/+1399
| | | | llvm-svn: 232728
* [Hexagon] ENDLOOP is a non-reversible conditional branchKrzysztof Parzyszek2015-03-191-0/+2
| | | | llvm-svn: 232725
* Internalize PEI. NFC.Benjamin Kramer2015-03-192-79/+48
| | | | llvm-svn: 232722
* [sparc] Small fix to r232719 to make 2007-12-17-InvokeAsm.ll pass on the ↵Daniel Sanders2015-03-191-0/+1
| | | | | | buildbot. llvm-svn: 232720
* [sparc] Only support the 'm' inline assembly memory constraint. NFC.Daniel Sanders2015-03-191-6/+0
| | | | | | | | | | | | | | | | Summary: SPARC doesn't seem to support any additional constraints. Therefore remove the target hook. No functional change intended. Reviewers: venkatra Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8214 llvm-svn: 232719
* [InstCombine] Don't fold a GEP into itself through a PHI nodeDaniel Jasper2015-03-191-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This can only occur (I think) through the back-edge of the loop. However, folding a GEP into itself means that the value of the previous iteration needs to be stored in the meantime, thus requiring an additional register variable to be live, but not actually achieving anything (the gep still needs to be executed once per loop iteration). The attached test case is derived from: typedef unsigned uint32; typedef unsigned char uint8; inline uint8 *f(uint32 value, uint8 *target) { while (value >= 0x80) { value >>= 7; ++target; } ++target; return target; } uint8 *g(uint32 b, uint8 *target) { target = f(b, f(42, target)); return target; } What happens is that the GEP stored in incptr2 is folded into itself through the loop's back-edge and the phi-node stored in loopptr, effectively incrementing the ptr by "2" in each iteration instead of "1". In this case, it is actually increasing the number of GEPs required as the GEP before the loop can't be folded away anymore. For comparison: With this patch: define i8* @test4(i32 %value, i8* %buffer) { entry: %cmp = icmp ugt i32 %value, 127 br i1 %cmp, label %loop.header, label %exit loop.header: ; preds = %entry br label %loop.body loop.body: ; preds = %loop.body, %loop.header %buffer.pn = phi i8* [ %buffer, %loop.header ], [ %loopptr, %loop.body ] %newval = phi i32 [ %value, %loop.header ], [ %shr, %loop.body ] %loopptr = getelementptr inbounds i8, i8* %buffer.pn, i64 1 %shr = lshr i32 %newval, 7 %cmp2 = icmp ugt i32 %newval, 16383 br i1 %cmp2, label %loop.body, label %loop.exit loop.exit: ; preds = %loop.body br label %exit exit: ; preds = %loop.exit, %entry %0 = phi i8* [ %loopptr, %loop.exit ], [ %buffer, %entry ] %incptr3 = getelementptr inbounds i8, i8* %0, i64 2 ret i8* %incptr3 } Without this patch: define i8* @test4(i32 %value, i8* %buffer) { entry: %incptr = getelementptr inbounds i8, i8* %buffer, i64 1 %cmp = icmp ugt i32 %value, 127 br i1 %cmp, label %loop.header, label %exit loop.header: ; preds = %entry br label %loop.body loop.body: ; preds = %loop.body, %loop.header %0 = phi i8* [ %buffer, %loop.header ], [ %loopptr, %loop.body ] %loopptr = phi i8* [ %incptr, %loop.header ], [ %incptr2, %loop.body ] %newval = phi i32 [ %value, %loop.header ], [ %shr, %loop.body ] %shr = lshr i32 %newval, 7 %incptr2 = getelementptr inbounds i8, i8* %0, i64 2 %cmp2 = icmp ugt i32 %newval, 16383 br i1 %cmp2, label %loop.body, label %loop.exit loop.exit: ; preds = %loop.body br label %exit exit: ; preds = %loop.exit, %entry %ptr2 = phi i8* [ %incptr2, %loop.exit ], [ %incptr, %entry ] %incptr3 = getelementptr inbounds i8, i8* %ptr2, i64 1 ret i8* %incptr3 } Review: http://reviews.llvm.org/D8245 llvm-svn: 232718
* Note that we don't support COFF on PPC.Rafael Espindola2015-03-191-0/+7
| | | | | | Should bring back the windows bots. llvm-svn: 232701
* Split the object streamer callback in one per file format.Rafael Espindola2015-03-1920-128/+118
| | | | | | | | | | | | | There are two main advantages to doing this * Targets that only need to handle one of the formats specially don't have to worry about the others. For example, x86 now only registers a constructor for the COFF streamer. * Changes to the arguments passed to one format constructor will not impact the other formats. llvm-svn: 232699
* SelectionDAGBuilder: update comment in HandlePHINodesInSuccessorBlocks.Hans Wennborg2015-03-191-2/+2
| | | | | | | From what I can tell, the code is checking for PHIs that expect any value from this block, not just constants. llvm-svn: 232697
* Do not track subregister liveness when it brings no benefitsMatthias Braun2015-03-196-11/+12
| | | | | | | | | | | Some subregisters are only to indicate different access sizes, while not providing any way to actually divide the register up into multiple disjunct parts. Avoid tracking subregister liveness in these cases as it is not beneficial. Differential Revision: http://reviews.llvm.org/D8429 llvm-svn: 232695
* SelectionDAGIsel: Fix comment about terminators being "handled below".Hans Wennborg2015-03-191-3/+2
| | | | | | That changed in r102128. llvm-svn: 232692
* [CodeGenPrepare] Remove broken, dead, code.Quentin Colombet2015-03-181-26/+6
| | | | | | NFC. llvm-svn: 232690
* two or more, use a for.Rafael Espindola2015-03-188-457/+225
| | | | llvm-svn: 232688
* Teach getDefaultFormat that we only support ELF on some architectures.Rafael Espindola2015-03-181-0/+17
| | | | | | | | | This should bring the windows bots back. It is a bit ugly, but it is better than what we had before: The triple would say that the object format was COFF, but llc/llvm-mc would produce an ELF. llvm-svn: 232683
* [X86][SSE] Avoid scalarization of v2i64 vector shifts (REAPPLIED)Simon Pilgrim2015-03-181-13/+24
| | | | | | | | Fixed broken tests. Differential Revision: http://reviews.llvm.org/D8416 llvm-svn: 232682
* [PowerPC] Correct typo in PPCInstrAltivec.tdBill Schmidt2015-03-181-1/+1
| | | | llvm-svn: 232681
* Revert "[X86][SSE] Avoid scalarization of v2i64 vector shifts" as itEric Christopher2015-03-181-24/+13
| | | | | | | | appears to have broken tests/bots. This reverts commit r232660. llvm-svn: 232670
* Revert "Add a TargetMachine local MCRegisterInfo and MCInstrInfo so that"Eric Christopher2015-03-182-15/+11
| | | | | | | | Committed too early. This reverts commit r232666. llvm-svn: 232667
* Add a TargetMachine local MCRegisterInfo and MCInstrInfo so thatEric Christopher2015-03-182-11/+15
| | | | | | | they can be used without a subtarget in constructing subtarget independent passes. llvm-svn: 232666
* Revert "Migrate the AArch64 TargetRegisterInfo to its TargetMachine"Eric Christopher2015-03-188-52/+48
| | | | | | | | | as we don't necessarily need to do this yet - though we could move the base class to the TargetMachine as it isn't subtarget dependent. This reverts commit r232103. llvm-svn: 232665
* Use WinEHPrepare to outline SEH finally blocksReid Kleckner2015-03-181-41/+109
| | | | | | | | | | | No outlining is necessary for SEH catch blocks. Use the blockaddr of the handler in place of the usual outlined function. Reviewers: majnemer, andrew.w.kaylor Differential Revision: http://reviews.llvm.org/D8370 llvm-svn: 232664
* [X86][SSE] Avoid scalarization of v2i64 vector shiftsSimon Pilgrim2015-03-181-13/+24
| | | | | | | | | | | | Currently v2i64 vectors shifts (non-equal shift amounts) are scalarized, costing 4 x extract, 2 x x86-shifts and 2 x insert instructions - and it gets even more awkward on 32-bit targets. This patch separately shifts the vector by both shift amounts and then shuffles the partial results back together, costing 2 x shuffles and 2 x sse-shifts instructions (+ 2 movs on pre-AVX hardware). Note - this patch only improves the SHL / LSHR logical shifts as only these are supported in SSE hardware. Differential Revision: http://reviews.llvm.org/D8416 llvm-svn: 232660
* Add a default implementation of createObjectStreamer.Rafael Espindola2015-03-184-42/+14
| | | | | | | This removes duplicated code from backends that don't need to do anything fancy. llvm-svn: 232658
* [Hexagon] Use pseudo-instructions for true/false predicate valuesKrzysztof Parzyszek2015-03-182-22/+24
| | | | llvm-svn: 232657
* Revert "[Hexagon] Use pseudo-instructions for true/false predicate values"Krzysztof Parzyszek2015-03-181-6/+23
| | | | | | | | This reverts r232650. Missed a piece of code in the previous commit. llvm-svn: 232656
* Handle X86::reloc_riprel_4byte in 32 bits mode.Rafael Espindola2015-03-181-0/+1
| | | | | | | | We can get there with .code64. Fixes pr22349. llvm-svn: 232651
* [Hexagon] Use pseudo-instructions for true/false predicate valuesKrzysztof Parzyszek2015-03-181-23/+6
| | | | llvm-svn: 232650
* [Hexagon] Intrinsics for circular and bit-reversed loads and storesKrzysztof Parzyszek2015-03-184-2/+398
| | | | llvm-svn: 232645
* [Hexagon] Handle ENDLOOP0 in InsertBranch and RemoveBranchKrzysztof Parzyszek2015-03-181-19/+28
| | | | llvm-svn: 232643
* Add support for .ifnes psuedo-op.Sid Manning2015-03-181-10/+22
| | | | llvm-svn: 232636
* [ARM] Align stack objects passed to memory intrinsicsJohn Brawn2015-03-183-0/+54
| | | | | | | | | | | | Memcpy, and other memory intrinsics, typically tries to use LDM/STM if the source and target addresses are 4-byte aligned. In CodeGenPrepare look for calls to memory intrinsics and, if the object is on the stack, 4-byte align it if it's large enough that we expect that memcpy would want to use LDM/STM to copy it. Differential Revision: http://reviews.llvm.org/D7908 llvm-svn: 232627
* Remove many superfluous SmallString::str() calls.Yaron Keren2015-03-187-19/+19
| | | | | | | | | | | | | | | Now that SmallString is a first-class citizen, most SmallString::str() calls are not required. This patch removes a whole bunch of them, yet there are lots more. There are two use cases where str() is really needed: 1) To use one of StringRef member functions which is not available in SmallString. 2) To convert to std::string, as StringRef implicitly converts while SmallString do not. We may wish to change this, but it may introduce ambiguity. llvm-svn: 232622
* [mips] Add itineraries for ext and ins instructions.Kai Nacke2015-03-182-2/+6
| | | | | | | | | | | Currently, there are no itineraries defined for ext and ins instructions. This patch adds these itineraries and uses them in the instruction definitions. Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D7209 llvm-svn: 232613
* [bpf] fix buildAlexei Starovoitov2015-03-181-1/+1
| | | | | | | | fix BPF backend build broken by r232429 Patch by Brenden Blanco llvm-svn: 232581
* Generate bit manipulation instructions on HexagonKrzysztof Parzyszek2015-03-181-0/+149
| | | | llvm-svn: 232577
* [SCEV] Make isImpliedCond smarter.Sanjoy Das2015-03-181-0/+44
| | | | | | | | | | | | | | | | | | Summary: This change teaches isImpliedCond to infer things like "X sgt 0" => "X - 1 sgt -1". The `ConstantRange` class has the logic to do the heavy lifting, this change simply gets ScalarEvolution to exploit that when reasonable. Depends on D8345 Reviewers: atrick Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8346 llvm-svn: 232576
* [ConstantRange] Split makeICmpRegion in two.Sanjoy Das2015-03-184-9/+20
| | | | | | | | | | | | | | | | | | | | Summary: This change splits `makeICmpRegion` into `makeAllowedICmpRegion` and `makeSatisfyingICmpRegion` with slightly different contracts. The first one is useful for determining what values some expression //may// take, given that a certain `icmp` evaluates to true. The second one is useful for determining what values are guaranteed to //satisfy// a given `icmp`. Reviewers: nlewycky Reviewed By: nlewycky Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8345 llvm-svn: 232575
* DAGCombiner: fold (xor (shl 1, x), -1) -> (rotl ~1, x)David Majnemer2015-03-181-0/+26
| | | | | | | | | | Targets which provide a rotate make it possible to replace a sequence of (XOR (SHL 1, x), -1) with (ROTL ~1, x). This saves an instruction on architectures like X86 and POWER(64). Differential Revision: http://reviews.llvm.org/D8350 llvm-svn: 232572
* COFF: Let globals with private linkage reside in their own sectionDavid Majnemer2015-03-174-4/+29
| | | | | | | | | | COFF COMDATs (for selection kinds other than 'select any') require at least one non-section symbol in the symbol table. Satisfy this by morally enhancing the linkage from private to internal. Differential Revision: http://reviews.llvm.org/D8394 llvm-svn: 232570
* Remove unneeded selection functions from HexagonISelDAGToDAGKrzysztof Parzyszek2015-03-171-189/+0
| | | | | | | - SelectSelect, and - SelectTruncate llvm-svn: 232569
* Fix bug while building FP16 constant vectors for AArch64Pirama Arumuga Nainar2015-03-171-2/+4
| | | | | | | | | | | | | | Summary: Building FP16 constant vectors caused the FP16 data to be bitcast to i64. This patch creates a BITCAST node with the correct value, and adds a test to verify correct handling. Reviewers: mcrosier Reviewed By: mcrosier Subscribers: mcrosier, jmolloy, ab, srhines, llvm-commits, rengolin, aemerson Differential Revision: http://reviews.llvm.org/D8369 llvm-svn: 232562
* Appease AArch64ISelLowering.cpp miscompiled by g++-4.7.2.NAKAMURA Takumi2015-03-171-0/+6
| | | | | | I will revert this when 4.7.3 is ready. llvm-svn: 232561
* XformToShuffleWithZero - Added clearer early outs and general tidy up. NFCISimon Pilgrim2015-03-171-31/+38
| | | | llvm-svn: 232557
* Selection DAG preprocessing on HexagonKrzysztof Parzyszek2015-03-171-2/+52
| | | | | | Simplify: (or (select c x 0) z) -> (select c (or x z) z) (or (select c 0 y) z) -> (select c z (or y z)) llvm-svn: 232553
* DebugInfo: Drop fake DW_TAG_expressionDuncan P. N. Exon Smith2015-03-171-1/+0
| | | | | | | | | | | | | Break MDExpression off of DebugNode (inherit directly from `MDNode`) and drop the fake `DW_TAG_expression` tag in the process. AFAICT, there's no real functionality change here. The tag was originally used by `DIDescriptor::isExpression()` to discriminate between `MDNode`s, but in the new hierarchy we don't need that. Fixes PR22780. llvm-svn: 232550
* Emit the offset directly instead of creating a dummy expression.Rafael Espindola2015-03-171-26/+1
| | | | | | | | We were creating an expression of the form (S+C)-S which is just C. Patch by Frédéric Riss. I just added the testcase. llvm-svn: 232549
* Revert "COFF: Let globals with private linkage reside in their own section"David Majnemer2015-03-173-31/+1
| | | | | | This reverts commit r232539. This was committed accidently. llvm-svn: 232543
* Internalize BitcodeReader. Not used outside of BitcodeReader.cpp.Benjamin Kramer2015-03-172-385/+342
| | | | | | NFC. llvm-svn: 232542
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