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* Refactor and improve the encodings/decodings for addrmode3 loads, and make ↵Owen Anderson2011-07-273-23/+41
| | | | | | the writeback operand always the first. llvm-svn: 136295
* Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil.Evan Cheng2011-07-274-23/+15
| | | | | | | | | This can happen in cases where TableGen generated asm matcher cannot check whether a register operand is in the right register class. e.g. mem operands. rdar://8204588 llvm-svn: 136292
* Fix llvm-mc handing of x86 instructions that take 8-bit unsigned immediates.Kevin Enderby2011-07-273-4/+35
| | | | | | | | | | | | llvm-mc gives an "invalid operand" error for instructions that take an unsigned immediate which have the high bit set such as: pblendw $0xc5, %xmm2, %xmm1 llvm-mc treats all x86 immediates as signed values and range checks them. A small number of x86 instructions use the imm8 field as a set of bits. This change only changes those instructions and where the high bit is not ignored. The others remain unchanged. llvm-svn: 136287
* ARM assembly parsing and encoding support for USAT and USAT16.Jim Grosbach2011-07-271-3/+5
| | | | | | Use range checked immediate operands for instructions. Add tests. llvm-svn: 136285
* Code generation for 'fence' instruction.Eli Friedman2011-07-2714-3/+108
| | | | llvm-svn: 136283
* Use BlockFrequency instead of uint32_t in BlockFrequencyInfo.Jakub Staszak2011-07-272-2/+2
| | | | llvm-svn: 136278
* ARM assembly parsing and encoding for UMULL.Jim Grosbach2011-07-271-1/+1
| | | | | | Fix parsing of the 's' suffix for the mnemonic. Add tests. llvm-svn: 136277
* Remove outdated FIXME comment.Devang Patel2011-07-271-1/+0
| | | | llvm-svn: 136275
* ARM assembly parsing and encoding for UMLAL.Jim Grosbach2011-07-271-1/+2
| | | | | | Fix parsing of the 's' suffix for the mnemonic. Add tests. llvm-svn: 136274
* Refuse to inline two functions which use different personality functions.Bill Wendling2011-07-271-0/+34
| | | | llvm-svn: 136269
* ARM parsing and encoding of SBFX and UBFX.Jim Grosbach2011-07-278-23/+19
| | | | | | | | | Encode the width operand as it encodes in the instruction, which simplifies the disassembler and the encoder, by using the imm1_32 operand def. Add a diagnostic for the context-sensitive constraint that the width must be in the range [1,32-lsb]. llvm-svn: 136264
* Refactor the STRT and STRBT instructions to distinguish between the ↵Owen Anderson2011-07-271-2/+30
| | | | | | register-addend and immediate-addend versions. Temporarily XFAIL the asm parsing tests for these instructions. llvm-svn: 136255
* Merge the contents from exception-handling-rewrite to the mainline.Bill Wendling2011-07-2719-24/+382
| | | | | | This adds the new instructions 'landingpad' and 'resume'. llvm-svn: 136253
* ARM assembly parsing and encoding for extend instructions.Jim Grosbach2011-07-272-0/+83
| | | | | | | Assembly parser handling for extend instruction rotate operands. Add tests for the sign extend instructions. llvm-svn: 136252
* Teach the ConstantMerge pass about alignment. Fixes PR10514!Nick Lewycky2011-07-271-8/+41
| | | | llvm-svn: 136250
* X86ISD::MEMBARRIER does not require SSE2; it doesn't actually generate any ↵Eli Friedman2011-07-271-1/+1
| | | | | | code, and all x86 processors will honor the required semantics. llvm-svn: 136249
* ARM assembly parsing aliases for extend instructions w/o rotate.Jim Grosbach2011-07-271-0/+22
| | | | llvm-svn: 136229
* ARM cleanup of remaining extend instructions.Jim Grosbach2011-07-272-171/+122
| | | | | | | | Refactor the rest of the extend instructions to not artificially distinguish between a rotate of zero and a rotate of any other value. Replace the by-zero versions with Pat<>'s for ISel. llvm-svn: 136226
* ARM extend instructions simplification.Jim Grosbach2011-07-275-89/+87
| | | | | | | | Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not have an 'r' and an 'r_rot' version, but just a single version with a rotate that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version. llvm-svn: 136225
* Optimize 96-bit division a little bit.Jakub Staszak2011-07-271-2/+3
| | | | llvm-svn: 136222
* Move static methods to the anonymous namespace.Jakub Staszak2011-07-271-2/+7
| | | | llvm-svn: 136221
* Trim includes.Frits van Bommel2011-07-271-12/+11
| | | | llvm-svn: 136218
* Explicitly cast narrowing conversions inside {}s that will become errors inJeffrey Yasskin2011-07-275-5/+7
| | | | | | C++0x. llvm-svn: 136211
* Revert r136156, which broke several buildbots.Dan Gohman2011-07-271-1/+14
| | | | llvm-svn: 136206
* Misc mid-level changes for new 'fence' instruction.Eli Friedman2011-07-274-5/+27
| | | | llvm-svn: 136205
* Minor simplification.Eli Friedman2011-07-271-2/+2
| | | | llvm-svn: 136202
* Move some code around to open opportunity for more shuffle matchingBruno Cardoso Lopes2011-07-271-18/+18
| | | | llvm-svn: 136201
* The vpermilps and vpermilpd have different behaviour regarding theBruno Cardoso Lopes2011-07-274-32/+140
| | | | | | | | | usage of the shuffle bitmask. Both work in 128-bit lanes without crossing, but in the former the mask of the high part is the same used by the low part while in the later both lanes have independent masks. Handle this properly and and add support for vpermilpd. llvm-svn: 136200
* Remove more dead code!Bruno Cardoso Lopes2011-07-271-15/+5
| | | | llvm-svn: 136199
* Fix AliasSetTracker so that it doesn't make any assumptions about ↵Eli Friedman2011-07-271-51/+46
| | | | | | instructions it doesn't know about (like the atomic instructions I'm adding). llvm-svn: 136198
* Support .code32 and .code64 in X86 assembler.Evan Cheng2011-07-278-13/+53
| | | | llvm-svn: 136197
* It is quiet possible that inlined function body is split into multiple ↵Devang Patel2011-07-271-16/+41
| | | | | | chunks of consequtive instructions. But, there is not any way to describe this in .debug_inline accelerator table used by gdb. However, describe non contiguous ranges of inlined function body appropriately using AT_range of DW_TAG_inlined_subroutine debug info entry. llvm-svn: 136196
* Add support for multi-way live range splitting.Jakob Stoklund Olesen2011-07-261-64/+165
| | | | | | | | | | | | | | | | | | | | | When splitting global live ranges, it is now possible to split for multiple destination intervals at once. Previously, we only had the main and stack intervals. Each edge bundle is assigned to a split candidate, and splitAroundRegion will insert copies between the candidate intervals and the stack interval as needed. The multi-way splitting is used to split around compact regions when enabled with -compact-regions. The best candidate register still gets all the bundles it wants, but everything outside the main interval is first split around compact regions before we create single-block intervals. Compact region splitting still causes some regressions, so it is not enabled by default. llvm-svn: 136186
* Print out the MBB live-in registers.Jakob Stoklund Olesen2011-07-261-0/+4
| | | | llvm-svn: 136178
* Eliminate copies of undefined values during coalescing.Jakob Stoklund Olesen2011-07-262-0/+53
| | | | | | | | | | These copies would coalesce easily, but the resulting value would be defined by a deleted instruction. Now we also remove the undefined value number from the destination register. This fixes PR10503. llvm-svn: 136174
* Add a neat little two's complement hack for x86.Benjamin Kramer2011-07-262-28/+38
| | | | | | | | | | On x86 we can't encode an immediate LHS of a sub directly. If the RHS comes from a XOR with a constant we can fold the negation into the xor and add one to the immediate of the sub. Then we can turn the sub into an add, which can be commuted and encoded efficiently. This code is generated for __builtin_clz and friends. llvm-svn: 136167
* Recognize unpckh* masks and match 256-bit versions. The new versions areBruno Cardoso Lopes2011-07-265-47/+90
| | | | | | | different from the previous 128-bit because they work in lanes. Update a few comments and add testcases llvm-svn: 136157
* Delete unnecessarily cautious LastCALLSEQ code.Dan Gohman2011-07-261-14/+1
| | | | llvm-svn: 136156
* ARM rot_imm printing adjustment.Jim Grosbach2011-07-263-9/+9
| | | | | | | Allow the rot_imm operand to be optional. This sets the stage for refactoring away the "rr" versions from the multiclasses and replacing them with Pat<>s. llvm-svn: 136154
* ARM cleanup of rot_imm encoding.Jim Grosbach2011-07-268-44/+47
| | | | | | | | Start of cleaning this up a bit. First step is to remove the encoder hook by storing the operand as the bits it'll actually encode to so it can just be directly used. Map it to the assembly source values 8/16/24 when we print it. llvm-svn: 136152
* Prevent x86-specific DAGCombine from creating nodes with illegal type (which ↵Eli Friedman2011-07-261-1/+2
| | | | | | could not be selected). Fixes a minor isel issue that was breaking the testcase from r136130. llvm-svn: 136148
* Remove one last reference to Target in MC library.Evan Cheng2011-07-261-1/+1
| | | | llvm-svn: 136145
* Split am2offset into register addend and immediate addend forms, necessary ↵Owen Anderson2011-07-267-50/+163
| | | | | | for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE. llvm-svn: 136141
* Update generated code to use new API of GetElementPtrInst::Create.Nicolas Geoffray2011-07-261-2/+1
| | | | llvm-svn: 136138
* Fix over-zealous rename from r136095.Jim Grosbach2011-07-261-3/+3
| | | | llvm-svn: 136132
* Add obvious missing case to switch. PR10497.Eli Friedman2011-07-261-2/+1
| | | | llvm-svn: 136130
* Use the correct for for the version. It's little endian and my brain isBill Wendling2011-07-261-1/+1
| | | | | | | obviously big endian. :-) PR10502 llvm-svn: 136111
* ARM diagnostics for ldrexd/stredx out of order paired register operands.Jim Grosbach2011-07-261-1/+39
| | | | llvm-svn: 136110
* Remove now unused patterns. 0 insertions(+), 98 deletions(-)Bruno Cardoso Lopes2011-07-261-98/+0
| | | | llvm-svn: 136109
* Cleanup old matching for PUNPCK* variantsBruno Cardoso Lopes2011-07-261-44/+42
| | | | llvm-svn: 136108
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