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| author | Owen Anderson <resistor@mac.com> | 2011-07-27 20:29:48 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-07-27 20:29:48 +0000 |
| commit | fa9e6d43a09b7d6855edc1d22d2fa4f409c5c837 (patch) | |
| tree | 9d5bebba300e63ee4c11b38fabe45d692af6fedc /llvm/lib | |
| parent | e1d209911f5ef271eae844357925f46606d968d3 (diff) | |
| download | bcm5719-llvm-fa9e6d43a09b7d6855edc1d22d2fa4f409c5c837.tar.gz bcm5719-llvm-fa9e6d43a09b7d6855edc1d22d2fa4f409c5c837.zip | |
Refactor the STRT and STRBT instructions to distinguish between the register-addend and immediate-addend versions. Temporarily XFAIL the asm parsing tests for these instructions.
llvm-svn: 136255
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrInfo.td | 32 |
1 files changed, 30 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td index 1061fbdbb33..4c6bace6399 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.td +++ b/llvm/lib/Target/ARM/ARMInstrInfo.td @@ -2090,22 +2090,50 @@ def STRD_POST: AI3stdpo<(outs GPR:$base_wb), // STRT, STRBT, and STRHT are for disassembly only. -def STRT : AI2stridxT<0, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr), +def STRTr : AI2stridxT<0, 0, (outs GPR:$Rn_wb), + (ins GPR:$Rt, ldst_so_reg:$addr), IndexModePost, StFrm, IIC_iStore_ru, "strt", "\t$Rt, $addr", "$addr.base = $Rn_wb", [/* For disassembly only; pattern left blank */]> { + let Inst{25} = 1; + let Inst{21} = 1; // overwrite + let Inst{4} = 0; + let AsmMatchConverter = "cvtStWriteBackRegAddrMode2"; +} + +def STRTi : AI2stridxT<0, 0, (outs GPR:$Rn_wb), + (ins GPR:$Rt, addrmode_imm12:$addr), + IndexModePost, StFrm, IIC_iStore_ru, + "strt", "\t$Rt, $addr", "$addr.base = $Rn_wb", + [/* For disassembly only; pattern left blank */]> { + let Inst{25} = 0; + let Inst{21} = 1; // overwrite + let AsmMatchConverter = "cvtStWriteBackRegAddrMode2"; +} + + +def STRBTr : AI2stridxT<1, 0, (outs GPR:$Rn_wb), + (ins GPR:$Rt, ldst_so_reg:$addr), + IndexModePost, StFrm, IIC_iStore_bh_ru, + "strbt", "\t$Rt, $addr", "$addr.base = $Rn_wb", + [/* For disassembly only; pattern left blank */]> { + let Inst{25} = 1; let Inst{21} = 1; // overwrite + let Inst{4} = 0; let AsmMatchConverter = "cvtStWriteBackRegAddrMode2"; } -def STRBT : AI2stridxT<1, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr), +def STRBTi : AI2stridxT<1, 0, (outs GPR:$Rn_wb), + (ins GPR:$Rt, addrmode_imm12:$addr), IndexModePost, StFrm, IIC_iStore_bh_ru, "strbt", "\t$Rt, $addr", "$addr.base = $Rn_wb", [/* For disassembly only; pattern left blank */]> { + let Inst{25} = 0; let Inst{21} = 1; // overwrite let AsmMatchConverter = "cvtStWriteBackRegAddrMode2"; } + def STRHT: AI3sthpo<(outs GPR:$base_wb), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm, IIC_iStore_bh_ru, "strht", "\t$Rt, $addr", "$addr.base = $base_wb", |
