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* [Hexagon] Add code to select QTRUE and QFALSEKrzysztof Parzyszek2018-02-093-0/+29
| | | | | | Fixes http://llvm.org/PR36320. llvm-svn: 324763
* [tablegen] Fixed few !foreach evaluation issues.Artem Belevich2018-02-091-41/+26
| | | | | | | | | | | | | | * !foreach on lists didn't evaluate operands of the RHS operator. This made nested operators silently fail. * A typo in the code could result in a wrong value substituted for an operation which produced a false '!foreach requires an operator' error. * Keep recursion over the DAG within ForeachHelper. This simplifies things a bit as we no longer need to pass the Type around in order to prevent recursion. Differential Revision: https://reviews.llvm.org/D43083 llvm-svn: 324758
* [ThinLTO] Teach ThinLTO about auto hide symbolsSteven Wu2018-02-091-0/+7
| | | | | | | | | | | | | | | | | | Summary: For symbols that has linkonce_odr linkage and unnamed_addr, it can be auto hide by linker to avoid weak external symbols. Teach ThinLTO to perform auto hide so it can safely promote linkonce_odr to weak symbols without breaking this nice property. Reviewers: tejohnson, mehdi_amini Reviewed By: tejohnson Subscribers: inglorion, eraman, rnk, pcc, llvm-commits Differential Revision: https://reviews.llvm.org/D43130 llvm-svn: 324757
* AMDGPU: Remove tied operand from si_elseMatt Arsenault2018-02-091-1/+0
| | | | llvm-svn: 324751
* Emit smaller exception tables for non-SJLJ mode.Rafael Espindola2018-02-091-8/+11
| | | | | | | | | | | * Use uleb128 for code offsets in the LSDA call site table. * Omit the TTBase offset if the type table is empty. This change can reduce the size of the DWARF/Itanium LSDA by about half. Patch by Ryan Prichard! llvm-svn: 324750
* Use assembler expressions to lay out the EH LSDA.Rafael Espindola2018-02-098-123/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rely on the assembler to finalize the layout of the DWARF/Itanium exception-handling LSDA. Rather than calculate the exact size of each thing in the LSDA, use assembler directives: To emit the offset to the TTBase label: .uleb128 .Lttbase0-.Lttbaseref0 .Lttbaseref0: To emit the size of the call site table: .uleb128 .Lcst_end0-.Lcst_begin0 .Lcst_begin0: ... call site table entries ... .Lcst_end0: To align the type info table: ... action table ... .balign 4 .long _ZTIi .long _ZTIl .Lttbase0: Using assembler directives simplifies the compiler and allows switching the encoding of offsets in the call site table from udata4 to uleb128 for a large code size savings. (This commit does not change the encoding.) The combination of the uleb128 followed by a balign creates an unfortunate dependency cycle that the assembler must sometimes resolve either by padding an LEB or by inserting zero padding before the type table. See PR35809 or GNU as bug 4029. Patch by Ryan Prichard! llvm-svn: 324749
* Reapply "AMDGPU: Add 32-bit constant address space"Matt Arsenault2018-02-0913-19/+86
| | | | | | This reverts r324494 and reapplies r324487. llvm-svn: 324747
* AMDGPU: Fix layering issueMatt Arsenault2018-02-096-21/+22
| | | | | | | Move utility function that depends on codegen. Fixes build with r324487 reapplied. llvm-svn: 324746
* [AArch64] Refactor stand alone methods (NFC)Evandro Menezes2018-02-092-142/+144
| | | | | | Make stand alone methods in AArch64InstrInfo static. llvm-svn: 324745
* [Hexagon] Express calling conventions via .td file instead of hand-codingKrzysztof Parzyszek2018-02-094-531/+255
| | | | | | Additionally, simplify the rest of the argument/parameter lowering code. llvm-svn: 324737
* [DebugInfo] Don't insert DEBUG_VALUE after terminatorsStefan Maksimovic2018-02-091-1/+1
| | | | | | | | | | | | | | r314974 introduced insertion of DEBUG_VALUEs after each redefinition of debug value register in the slot index range. In case the instruction redefining the debug value register was a terminator, machine verifier would complain since it enforces the rule of no non-terminator instructions following the first terminator. Differential Revision: https://reviews.llvm.org/D42801 llvm-svn: 324734
* [SelectionDAG] Provide adequate register class for RegisterSDNodeStefan Maksimovic2018-02-091-1/+16
| | | | | | | | | | When adding operands to machine instructions in case of RegisterSDNodes, generate a COPY node in case the register class does not match the one in the instruction definition. Differental Revision: https://reviews.llvm.org/D35561 llvm-svn: 324733
* [ELF] Print the .type assembly directive correctly for STT_NOTYPEOliver Stannard2018-02-091-1/+1
| | | | | | | | | | The llvm assembly parser and gas both accept "@notype" in the .type assembly directive, but we were printing it as "@no_type", which isn't accepted by either assembler. Differential revision: https://reviews.llvm.org/D43116 llvm-svn: 324731
* [InstCombine] Add constant vector support for X udiv C, where C >= signbitSimon Pilgrim2018-02-091-8/+6
| | | | llvm-svn: 324728
* [CodeGen] Optimize AccelTablePavel Labath2018-02-091-20/+17
| | | | | | | | | | | | | | | | | Summary: The class contained arrays of two structures (DataArray and HashData). These structures were in 1:1 correspondence, and one of them contained pointers to the other (and *both* contained a "Name" field). By merging these two structures into one, we can save a bit of space without negatively impacting much of anything. Reviewers: JDevlieghere, aprantl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D43073 llvm-svn: 324724
* [AArch64] Return true in enableMultipleCopyHints().Jonas Paulsson2018-02-091-0/+2
| | | | | | | | | | Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Martin Storsjö llvm-svn: 324720
* Rename and move utility function getLatchPredicateForGuard. NFC.Serguei Katkov2018-02-092-30/+27
| | | | | | | Rename getLatchPredicateForGuard to more common name getFlippedStrictnessPredicate and move it to ICmpInst class. llvm-svn: 324717
* [AMDGPU] More descriptive names in the memory legalizerStanislav Mekhanoshin2018-02-091-19/+20
| | | | | | | | NFC. Differential Revision: https://reviews.llvm.org/D43054 llvm-svn: 324712
* LTO: Include live bit in ThinLTO cache key.Peter Collingbourne2018-02-091-0/+1
| | | | | | | | | | As of r323633, this bit started controlling whether symbol definitions appear in object files, and it also became sensitive to the prevailing bit, so it needs to be included in the key. Differential Revision: https://reviews.llvm.org/D43109 llvm-svn: 324711
* [X86] Simplify some code in lowerV4X128VectorShuffle and ↵Craig Topper2018-02-091-11/+9
| | | | | | | | lowerV2X128VectorShuffle Previously we extracted two subvectors and concatenate. But the concatenate will be lowered to two insert subvectors. Then DAG combine will merge once of the inserts and one of the extracts back into the original vector. We might as well just directly use one extract and one insert. llvm-svn: 324710
* [X86] Teach shuffle lowering to recognize 128/256 bit insertions into a zero ↵Craig Topper2018-02-091-9/+35
| | | | | | | | vector. This regresses a couple cases in the shuffle combining test. But those cases use intrinsics that InstCombine knows how to turn into a generic shuffle earlier. This should give opportunities to fold this earlier in InstCombine or DAG combine. llvm-svn: 324709
* [ORC] Remove Layer handles from the layer concept.Lang Hames2018-02-092-105/+56
| | | | | | | | | Handles were returned by addModule and used as keys for removeModule, findSymbolIn, and emitAndFinalize. Their job is now subsumed by VModuleKeys, which simplify resource management by providing a consistent handle across all layers. llvm-svn: 324700
* [GISel]: Verify COPIES involving generic registers.Aditya Nandakumar2018-02-091-0/+30
| | | | | | | | | | | | Add verification for copies involving generic registers if they are compatible - ie if it is a generic copy, then the types are the same, and if a COPY b/w generic and target virtual register, then the sizes should be the same. Only checks if there are no sub registers involved for now. https://reviews.llvm.org/D37775 llvm-svn: 324696
* [CodeGen] Unify the syntax of MBB liveins in MIR and -debug outputFrancis Visoiu Mistrih2018-02-092-7/+14
| | | | | | | | | | | Instead of: Live Ins: %r0 %r1 print: liveins: %r0, %r1 llvm-svn: 324694
* [hwasan] Fix kernel instrumentation of stack.Evgeniy Stepanov2018-02-091-3/+21
| | | | | | | | | | | | | | | Summary: Kernel addresses have 0xFF in the most significant byte. A tag can not be pushed there with OR (tag << 56); use AND ((tag << 56) | 0x00FF..FF) instead. Reviewers: kcc, andreyknvl Subscribers: srhines, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D42941 llvm-svn: 324691
* [CodeGen] Don't compute BranchProbability for MBB::printFrancis Visoiu Mistrih2018-02-091-15/+19
| | | | | | | Avoid re-computing BP only to print successor probabilities in -debug printing. llvm-svn: 324690
* [CodeGen] Only print successors when the list is not emptyFrancis Visoiu Mistrih2018-02-091-21/+24
| | | | | | Follow-up of r324685. llvm-svn: 324686
* [CodeGen] Unify the syntax of MBB successors in MIR and -debug outputFrancis Visoiu Mistrih2018-02-091-11/+24
| | | | | | | | | | | Instead of: Successors according to CFG: %bb.6(0x12492492 / 0x80000000 = 14.29%) print: successors: %bb.6(0x12492492); %bb.6(14.29%) llvm-svn: 324685
* [CodeGen] Move printing '\n' from MachineInstr::print to ↵Francis Visoiu Mistrih2018-02-085-24/+41
| | | | | | | | | MachineBasicBlock::print MBB.print wasn't printing it, but the MIRPrinter is printing it. The goal is to unify that as much as possible. llvm-svn: 324681
* [Lanai] Code model dictates section selection.Jacques Pienaar2018-02-081-7/+5
| | | | | | Always use the small section when the small code model is specified. llvm-svn: 324679
* Use a stable topological sort in DwarfCompileUnit::createScopeChildrenDIE()Adrian Prantl2018-02-081-13/+67
| | | | | | | | | | | | This addresses review feedback for D42940. The topological sort is slightly more expensive but it can now also detect cycles in the dependencies and actually works correctly. rdar://problem/37217988 Differential Review: https://reviews.llvm.org/D43036 llvm-svn: 324677
* [DWARFv5] Fix dumper to show the file table starts at index 0.Paul Robinson2018-02-081-1/+4
| | | | | | | | Emitting the correct (root of compilation) file at index 0 will be posted for review later; I wanted to get this minor change out of the way first. llvm-svn: 324669
* AMDGPU: Process SDWA block at a timeMatt Arsenault2018-02-081-32/+31
| | | | | | | | | | Right now this loops over the entire function every time there is a change, which is not very efficient. There's no practical reason to track this so globally, since the code motion optimization passes should be sinking instructions with single uses and the pass currently will not fold with multiple uses. llvm-svn: 324667
* AMDGPU: Minor cleanupsMatt Arsenault2018-02-081-3/+4
| | | | | | Column limit, typo, unnecessary reference llvm-svn: 324666
* [GlobalISel][X86] Fixing failures after https://reviews.llvm.org/D37775Alexander Ivchenko2018-02-084-11/+110
| | | | | | | | | | | | | | The patch essentially makes sure that X86CallLowering adds proper G_COPY/G_TRUNC and G_ANYEXT/G_COPY when we are doing lowering of arguments/returns for floating point values passed on registers. Tests are updated accordingly Reviewed By: qcolombet Differential Revision: https://reviews.llvm.org/D42287 llvm-svn: 324665
* [GlobalIsel][X86] Making {G_IMPLICIT_DEF, s128} legalAlexander Ivchenko2018-02-081-0/+3
| | | | | | | | | | | The patch is a split from D42287 and is related to fixing failures after https://reviews.llvm.org/D37775 Reviewed By: qcolombet Differential Revision: https://reviews.llvm.org/D42287 llvm-svn: 324664
* [X86] Improve combineCastedMaskArithmetic to fold (bitcast (vXi1 (and/or/xor ↵Craig Topper2018-02-081-7/+27
| | | | | | | | X, C)))->(vXi1 (and/or/xor (bitcast X), (bitcast C)) where C is a constant build_vector. Most vxi1 constant build vectors have to be implemented in the scalar domain anyway so we'll probably end up with a cast there later. But by then its too late to do the combine to get rid of it. llvm-svn: 324662
* [X86] Add DAG combine to constant fold a bitcast of a vXi1 constant ↵Craig Topper2018-02-081-0/+14
| | | | | | build_vector into a scalar integer. llvm-svn: 324661
* [ThinLTO] Skip BlockAddresses while replacing uses in function import.Dmitry Mikulin2018-02-081-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D43027 llvm-svn: 324658
* [DSan] Update uses of memory intrinsic get/setAlignment to new API (NFC)Daniel Neilson2018-02-081-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This change is part of step five in the series of changes to remove alignment argument from memcpy/memmove/memset in favour of alignment attributes. In particular, this changes the DataFlowSanitizer pass to cease using the old get/setAlignment() API of MemoryIntrinsic in favour of getting source & dest specific alignments through the new API. Steps: Step 1) Remove alignment parameter and create alignment parameter attributes for memcpy/memmove/memset. ( rL322965, rC322964, rL322963 ) Step 2) Expand the IRBuilder API to allow creation of memcpy/memmove with differing source and dest alignments. ( rL323597 ) Step 3) Update Clang to use the new IRBuilder API. ( rC323617 ) Step 4) Update Polly to use the new IRBuilder API. ( rL323618 ) Step 5) Update LLVM passes that create memcpy/memmove calls to use the new IRBuilder API, and those that use use MemIntrinsicInst::[get|set]Alignment() to use [get|set]DestAlignment() and [get|set]SourceAlignment() instead. ( rL323886, rL323891, rL324148, rL324273, rL324278, rL324384, rL324395, rL324402, rL324626, rL324642, rL324653 ) Step 6) Remove the single-alignment IRBuilder API for memcpy/memmove, and the MemIntrinsicInst::[get|set]Alignment() methods. Reference http://lists.llvm.org/pipermail/llvm-dev/2015-August/089384.html http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20151109/312083.html llvm-svn: 324654
* [ASan] Update uses of IRBuilder::CreateMemCpy to new API (NFC)Daniel Neilson2018-02-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This change is part of step five in the series of changes to remove alignment argument from memcpy/memmove/memset in favour of alignment attributes. In particular, this changes the AddressSanitizer pass to cease using The old IRBuilder CreateMemCpy single-alignment API in favour of the new API that allows setting source and destination alignments independently. Steps: Step 1) Remove alignment parameter and create alignment parameter attributes for memcpy/memmove/memset. ( rL322965, rC322964, rL322963 ) Step 2) Expand the IRBuilder API to allow creation of memcpy/memmove with differing source and dest alignments. ( rL323597 ) Step 3) Update Clang to use the new IRBuilder API. ( rC323617 ) Step 4) Update Polly to use the new IRBuilder API. ( rL323618 ) Step 5) Update LLVM passes that create memcpy/memmove calls to use the new IRBuilder API, and those that use use MemIntrinsicInst::[get|set]Alignment() to use [get|set]DestAlignment() and [get|set]SourceAlignment() instead. ( rL323886, rL323891, rL324148, rL324273, rL324278, rL324384, rL324395, rL324402, rL324626, rL324642 ) Step 6) Remove the single-alignment IRBuilder API for memcpy/memmove, and the MemIntrinsicInst::[get|set]Alignment() methods. Reference http://lists.llvm.org/pipermail/llvm-dev/2015-August/089384.html http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20151109/312083.html llvm-svn: 324653
* Revert "WIP: [DAGCombiner] Assert that debug info is preserved"Vedant Kumar2018-02-081-31/+4
| | | | | | This reverts commit r324648. It was committed accidentally. llvm-svn: 324650
* WIP: [DAGCombiner] Assert that debug info is preservedVedant Kumar2018-02-081-4/+31
| | | | llvm-svn: 324648
* [X86] Remove kortest intrinsics and replace with native IR.Craig Topper2018-02-082-10/+15
| | | | llvm-svn: 324646
* [X86] Support 'V' register operand modifierDavid Woodhouse2018-02-081-1/+10
| | | | | | | | This allows the register name to be printed without the leading '%'. This can be used for emitting calls to the retpoline thunks from inline asm. llvm-svn: 324645
* [MSan] Update uses of IRBuilder::CreateMemCpy to new API (NFC)Daniel Neilson2018-02-081-19/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This change is part of step five in the series of changes to remove alignment argument from memcpy/memmove/memset in favour of alignment attributes. In particular, this changes the MemorySanitizer pass to cease using the old IRBuilder CreateMemCpy single-alignment APIs in favour of the new API that allows setting source and destination alignments independently. Steps: Step 1) Remove alignment parameter and create alignment parameter attributes for memcpy/memmove/memset. ( rL322965, rC322964, rL322963 ) Step 2) Expand the IRBuilder API to allow creation of memcpy/memmove with differing source and dest alignments. ( rL323597 ) Step 3) Update Clang to use the new IRBuilder API. ( rC323617 ) Step 4) Update Polly to use the new IRBuilder API. ( rL323618 ) Step 5) Update LLVM passes that create memcpy/memmove calls to use the new IRBuilder API, and those that use use MemIntrinsicInst::[get|set]Alignment() to use [get|set]DestAlignment() and [get|set]SourceAlignment() instead. ( rL323886, rL323891, rL324148, rL324273, rL324278, rL324384, rL324395, rL324402, rL324626 ) Step 6) Remove the single-alignment IRBuilder API for memcpy/memmove, and the MemIntrinsicInst::[get|set]Alignment() methods. Reference http://lists.llvm.org/pipermail/llvm-dev/2015-August/089384.html http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20151109/312083.html llvm-svn: 324642
* [InstCombine] visitSRem - use m_Negative(APInt) helper. NFCI.Simon Pilgrim2018-02-081-1/+1
| | | | llvm-svn: 324636
* [SelectionDAG] Add a helper function for creating a boolean constant based ↵Craig Topper2018-02-082-82/+82
| | | | | | | | | | | | | on the target's boolean content Many in SimplifySetCC and FoldSetCC try to create true or false constants. Some of them query getBooleanContents to figure out whether to use all ones or just 1 for true. But many places do not check and just use 1 without ensuring the VT has an i1 scalar type. Note sure if those places only trigger before type legalization so they only see an i1 type? To cleanup the inconsistency and reduce some duplicated code, this patch adds a getBoolConstant method to SelectionDAG that takes are of querying getBooleanContents and doing the right thing. Differential Revision: https://reviews.llvm.org/D43037 llvm-svn: 324634
* [InstCombine] Add m_Negative pattern matchingSimon Pilgrim2018-02-081-2/+1
| | | | | | Allows us to add non-uniform constant vector support for "X urem C -> X < C ? X : X - C, where C >= signbit." llvm-svn: 324631
* Use ranged for loops in TypeFinder.cpp, NFCVedant Kumar2018-02-081-30/+20
| | | | llvm-svn: 324628
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