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authorKrzysztof Parzyszek <kparzysz@codeaurora.org>2018-02-09 19:10:46 +0000
committerKrzysztof Parzyszek <kparzysz@codeaurora.org>2018-02-09 19:10:46 +0000
commit9b48e8d233e9013dc6a38e628350c6d76c46a58a (patch)
tree1282627a179dd49a1986fdc27a8d1128f3fb7fc9 /llvm/lib
parent3959041d4ec6f08dd4c9b11f0e21069a7a836c08 (diff)
downloadbcm5719-llvm-9b48e8d233e9013dc6a38e628350c6d76c46a58a.tar.gz
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[Hexagon] Add code to select QTRUE and QFALSE
Fixes http://llvm.org/PR36320. llvm-svn: 324763
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp14
-rw-r--r--llvm/lib/Target/Hexagon/HexagonPatternsHVX.td7
-rw-r--r--llvm/lib/Target/Hexagon/HexagonPseudo.td8
3 files changed, 29 insertions, 0 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index f313f2fc867..99436aae201 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -1124,6 +1124,20 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
MBB.erase(MI);
return true;
}
+ case Hexagon::PS_qtrue: {
+ BuildMI(MBB, MI, DL, get(Hexagon::V6_veqw), MI.getOperand(0).getReg())
+ .addReg(Hexagon::V0, RegState::Undef)
+ .addReg(Hexagon::V0, RegState::Undef);
+ MBB.erase(MI);
+ return true;
+ }
+ case Hexagon::PS_qfalse: {
+ BuildMI(MBB, MI, DL, get(Hexagon::V6_vgtw), MI.getOperand(0).getReg())
+ .addReg(Hexagon::V0, RegState::Undef)
+ .addReg(Hexagon::V0, RegState::Undef);
+ MBB.erase(MI);
+ return true;
+ }
case Hexagon::PS_vmulw: {
// Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
unsigned DstReg = MI.getOperand(0).getReg();
diff --git a/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td b/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
index 0e5436411cf..50081799bf7 100644
--- a/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
+++ b/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
@@ -291,6 +291,13 @@ let Predicates = [UseHVX] in {
def: Pat<(srl HVI16:$Vs, HVI16:$Vt), (V6_vlsrhv HvxVR:$Vs, HvxVR:$Vt)>;
def: Pat<(srl HVI32:$Vs, HVI32:$Vt), (V6_vlsrwv HvxVR:$Vs, HvxVR:$Vt)>;
+ def: Pat<(VecQ8 (qtrue)), (PS_qtrue)>;
+ def: Pat<(VecQ16 (qtrue)), (PS_qtrue)>;
+ def: Pat<(VecQ32 (qtrue)), (PS_qtrue)>;
+ def: Pat<(VecQ8 (qfalse)), (PS_qfalse)>;
+ def: Pat<(VecQ16 (qfalse)), (PS_qfalse)>;
+ def: Pat<(VecQ32 (qfalse)), (PS_qfalse)>;
+
def: Pat<(vnot HQ8:$Qs), (V6_pred_not HvxQR:$Qs)>;
def: Pat<(vnot HQ16:$Qs), (V6_pred_not HvxQR:$Qs)>;
def: Pat<(vnot HQ32:$Qs), (V6_pred_not HvxQR:$Qs)>;
diff --git a/llvm/lib/Target/Hexagon/HexagonPseudo.td b/llvm/lib/Target/Hexagon/HexagonPseudo.td
index b2d66317b66..37610bc6445 100644
--- a/llvm/lib/Target/Hexagon/HexagonPseudo.td
+++ b/llvm/lib/Target/Hexagon/HexagonPseudo.td
@@ -448,6 +448,14 @@ def PS_wselect: VSELInst<(outs HvxWR:$dst),
(ins PredRegs:$src1, HvxWR:$src2, HvxWR:$src3), V6_vccombine>,
Requires<[HasV60T,UseHVX]>;
+let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1,
+ isCodeGenOnly = 1 in {
+ def PS_qtrue: InstHexagon<(outs HvxQR:$Qd), (ins), "", [], "",
+ V6_veqw.Itinerary, TypeCVI_VA>;
+ def PS_qfalse: InstHexagon<(outs HvxQR:$Qd), (ins), "", [], "",
+ V6_vgtw.Itinerary, TypeCVI_VA>;
+}
+
// Store predicate.
let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13,
isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
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