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* [cfi] Add flag to always generate .debug_frameDavid Candler2019-10-3111-23/+24
| | | | | | | | | This adds a flag to LLVM and clang to always generate a .debug_frame section, even if other debug information is not being generated. In situations where .eh_frame would normally be emitted, both .debug_frame and .eh_frame will be used. Differential Revision: https://reviews.llvm.org/D67216
* [yaml2obj/obj2yaml] - Add support for SHT_GNU_HASH section.georgerim2019-10-312-0/+115
| | | | | | | This adds parsing and dumping support for GNU hash sections. They are described nicely here: https://blogs.oracle.com/solaris/gnu-hash-elf-sections-v2 Differential revision: https://reviews.llvm.org/D69399
* Revert "[SLP] Vectorize jumbled stores."Haojian Wu2019-10-311-91/+16
| | | | | | This reverts commit 21d498c9c0f32dcab5bc89ac593aa813b533b43a. This commit causes some crashes on some targets.
* [MustExecute] Silence clang warning about unused captured 'this'Mikael Holmen2019-10-311-2/+2
| | | | | | | | | | | | New code introduced in fe799c97fa caused clang to complain with ../lib/Analysis/MustExecute.cpp:360:34: error: lambda capture 'this' is not used [-Werror,-Wunused-lambda-capture] GetterTy<LoopInfo> LIGetter = [this](const Function &F) { ^~~~ ../lib/Analysis/MustExecute.cpp:365:44: error: lambda capture 'this' is not used [-Werror,-Wunused-lambda-capture] GetterTy<PostDominatorTree> PDTGetter = [this](const Function &F) { ^~~~ 2 errors generated.
* [Attributor][NFCI] Improve the usage of IntegerStatesJohannes Doerfert2019-10-311-12/+8
| | | | | Setting the upper bound directly in the state can be beneficial and simplifies the logic. This also exposed more copy&paste type errors.
* [Attributor] Make liveness "edge-based"Johannes Doerfert2019-10-311-126/+186
| | | | | | | | | | | | | | | | Summary: If control is transferred to a successor is the key question when it comes to liveness. The new implementation puts that question in the focus and thereby providing a clean way to assume certain CFG edges are dead or instructions will not transfer control. Reviewers: sstefan1, uenoku Subscribers: hiraditya, bollu, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69605
* [Attributor] Liveness for valuesJohannes Doerfert2019-10-311-31/+321
| | | | | | | | | | | | | | | | | | | | | | | Summary: This patch introduces liveness (AAIsDead) for all positions, thus for all kinds of values. For now, we say an instruction is dead if it would be removed assuming all users are dead. A call site return is different as we just look at the users. If all call site returns have been eliminated, the return values can return undef instead of their original value, eliminating uses. We try to recursively delete dead instructions now and we introduce a simple check interface for use-traversal. This is the idea tried out in D68626 but implemented in the right way. Reviewers: uenoku, sstefan1 Subscribers: hiraditya, bollu, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68925
* [Attributor][NFC] Do not delete dead blocks but "clear" themJohannes Doerfert2019-10-311-3/+6
| | | | | | | Deleting blocks will require us to deal with dead edges, e.g., `br i1 false, label %live, label %dead` explicitly. For now we just clear the blocks and move on. This will be revisited once we actually fold branches.
* [MustExecute] Forward iterate over conditional branchesJohannes Doerfert2019-10-311-1/+187
| | | | | | | | | | | | | | | | | | | Summary: If a conditional branch is encountered we can try to find a join block where the execution is known to continue. This means finding a suitable block, e.g., the immediate post dominator of the conditional branch, and proofing control will always reach that block. This patch implements different techniques that work with and without provided analysis. Reviewers: uenoku, sstefan1, hfinkel Subscribers: hiraditya, bollu, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68933
* [Attributor] Add "free"-based heap2stack deductionJohannes Doerfert2019-10-301-18/+43
| | | | | | | | | | | | | | | Summary: If there is a unique free of the allocated that has to be reached from the malloc, we can apply the heap-2-stack transformation even if the pointer escapes. Reviewers: hfinkel, sstefan1, uenoku Subscribers: hiraditya, bollu, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68958
* [AArch64][SVE] Add patterns for some integer vector instructionsEhsan Amiri2019-10-303-40/+85
| | | | | | | | | | | | Add pattern matching for SVE vector instructions: -- add, sub, and, or, xor instructions -- sqadd, uqadd, sqsub, uqsub target-independent intrinsics -- bic intrinsics -- predicated add, sub, subr intrinsics Patch Review: https://reviews.llvm.org/D69128 Patch authored by: dancgr (Danilo Carvalho Grael)
* [Attributor][NFC] Eagerly mark attributes as fixed.Johannes Doerfert2019-10-301-4/+14
| | | | | | If an attribute did not query any optimistic (=non-fixed) information to justify its state, we know the attribute state will not change anymore. Thus, we can indicate an optimistic fixpoint.
* [Attributor][NFC] Do not record dependences on fixed attributesJohannes Doerfert2019-10-301-0/+6
| | | | | Since fixed values cannot change, we do not need to wait for it to happen, we will never notify the dependent attribute anyway.
* [Attributor][NFC] Simplify the IRPosition interfaceJohannes Doerfert2019-10-301-4/+6
| | | | | | | We pretended IRPosition came either as mutable or immutable objects while they are basically always immutable, with a single (existing) unfortunate exceptions. This patch cleans up the uses to deal with the immutable version.
* [GISel][CombinerHelper] Combine shuffle_vector scalar to build_vectorQuentin Colombet2019-10-301-2/+2
| | | | | | | | | | Teach the combiner helper how to replace shuffle_vector of scalars into build_vector. I am not particularly happy about having to add this combine, but we currently get those from <1 x iN> from the IR. Bonus: This fixes an assert in the shuffle_vector combines since before this patch, we were expecting vector types.
* [ThinLTO/WPD] Fix index-based WPD for available_externally vtablesTeresa Johnson2019-10-301-8/+26
| | | | | | | | | | | | | | | | | | | | | | Summary: Clang does not add type metadata to available_externally vtables. When choosing a summary to look at for virtual function definitions, make sure we skip summaries for any available externally vtables as they will not describe any virtual function functions, which are only summarized in the presence of type metadata on the vtable def. Simply look for the corresponding strong def's summary. Also add handling for same-named local vtables with the same GUID because of same-named files without enough distinguishing path. In that case we return a conservative result with no devirtualization. Reviewers: pcc, davidxl, evgeny777 Subscribers: mehdi_amini, inglorion, hiraditya, steven_wu, dexonsmith, arphaman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69452
* [JITLink] Move block ownership from LinkGraph to Section.Lang Hames2019-10-301-4/+0
| | | | This enables easy iteration over blocks in a specific section.
* Revert "[CodeView] Add option to disable inline line tables."Amy Huang2019-10-301-30/+11
| | | | | | because it breaks compiler-rt tests. This reverts commit 6d03890384517919a3ba7fe4c35535425f278f89.
* [CodeView] Add option to disable inline line tables.Amy Huang2019-10-301-11/+30
| | | | | | | | | | | | | | | | | Summary: This adds a clang option to disable inline line tables. When it is used, the inliner uses the call site as the location of the inlined function instead of marking it as an inline location with the function location. See https://bugs.llvm.org/show_bug.cgi?id=42344 Reviewers: rnk Subscribers: hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D67723
* [InstCombine] keep assumption before sinking callstyker2019-10-311-2/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: in the following C code the branch is not removed by clang in O3. ``` int f1(char* p) { int i1 = __builtin_strlen(p); if (!p) return -1; return i1; } ``` The issue is that the call to strlen is sunk to the following block by instcombine. In its new place the call to strlen doesn't dominate the use in the icmp anymore so value tracking can't see that p cannot be null. This patch resolves the issue by inserting an assumption at the place of the call before sinking a call when that call can be used to prove an argument to be nonnull. This resolves this issue at O3. Reviewers: majnemer, xbolva00, fhahn, jdoerfert, spatel, efriedma Reviewed By: jdoerfert Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69477
* Fix -Wsign-compare warning with clang-clReid Kleckner2019-10-301-2/+2
| | | | | | off_t apparently is just "long" on Win64, which is 32-bits, and therefore not long enough to compare with UINT32_MAX. Use auto to follow the surrounding code. uint64_t would also be fine.
* [X86] Model MXCSR for all SSE instructionsCraig Topper2019-10-304-51/+97
| | | | | | | | | | | | | | | This patch adds MXCSR as a reserved physical register and models its use by X86 SSE instructions. It also adds flag "mayRaiseFPException" for the instructions that possibly can raise FP exception according to the architecture definition. Following what SystemZ and other targets does, only the current rounding modes and the IEEE exception masks are modeled. *Changes* of the MXCSR due to exceptions are not modeled. Patch by Pengfei Wang Differential Revision: https://reviews.llvm.org/D68121
* AMDGPU: Disallow spill folding with m0 copiesMatt Arsenault2019-10-302-0/+42
| | | | | | | | | | readlane and writelane instructions are not allowed to use m0 as the data operand, so spilling them is tricky and would require an intermediate SGPR to spill it. Constrain the virtual register class in this caes to disallow the inline spiller from folding the m0 operand directly into the spill instruction. I copied this hack from AArch64 which has the same problem for $sp.
* AMDGPU: Don't fold S_NOPs with implicit operandsMatt Arsenault2019-10-301-1/+3
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* RegAllocFast: Use RegisterMatt Arsenault2019-10-301-69/+69
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* [X86] Rewrite hasReassociableOperands and setSpecialOperandAttr to not ↵Craig Topper2019-10-301-28/+19
| | | | | | hardcode number of operands or position of the EFLAGS operand. This makes the code immune to the MXCSR addition in D68121.
* [clang][llvm] Obsolete Exynos M1 and M2Evandro Menezes2019-10-306-896/+5
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* [JITLink] Add a utility for splitting blocks at a given index.Lang Hames2019-10-301-0/+79
| | | | | | | | LinkGraph::splitBlock will split a block at a given index, returning a new block covering the range [ 0, index ) and modifying the original block to cover the range [ index, original-block-size ). Block addresses, content, edges and symbols will be updated as necessary. This utility will be used in upcoming improvements to JITLink's eh-frame support.
* [AArch64] Remove overlapping scheduling definitions (NFC)Evandro Menezes2019-10-301-19/+0
| | | | | | | | | | The scheduling definitions for ASIMD transpose and zipping overlapped with others a few lines below. Somehow, they didn't raise errors before. There seem to be other overlapping definitions. Somehow, they still don't raise errors. Differential revision: https://reviews.llvm.org/D68353
* [PowerPC][AIX] Adds support for writing the data section in object filesjasonliu2019-10-301-1/+8
| | | | | | | | | | | | | | | | | | | | Adds support for generating the XCOFF data section in object files for global variables with initialization. Merged aix-xcoff-common.ll into aix-xcoff-data.ll. Changed variable name charr to chrarray in the test case to test if readobj works with 8-character names. Authored by: xingxue Reviewers: hubert.reinterptrtcast, sfertile, jasonliu, daltenty, Xiangling_L. Reviewed by: hubert.reinterpretcast, sfertile, daltenty. Subscribers: DiggerLin, Wuzish, nemanjai, hiraditya, MaskRay, jsji, shchenz, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67125
* [DebugInfo][DAG] Distinguish different kinds of location indirectionJeremy Morse2019-10-301-5/+19
| | | | | | | | | | | | | | | | | | From SelectionDAGs point of view, debug variable locations specified with dbg.declare and dbg.addr are indirect -- they specify the address of something. But calling conventions might mean that a Value is placed on the stack somewhere, and this too is indirection. Previously this was mixed up in the "IsIndirect" field of DBG_VALUE insts; this patch separates them by encoding the indirection in a DIExpression. If we have a dbg.declare or dbg.addr, then the expression produces an address that then becomes a DWARF memory location. We can represent this by putting a DW_OP_deref on the _end_ of the expression. If a Value has been placed on the stack, then we need to put a DW_OP_deref on the _start_ of the expression, to load the Value from the stack and have the rest of the expression operate on it. Differential Revision: https://reviews.llvm.org/D69028
* [LegacyPassManager] Delete BasicBlockPass/Manager.Alina Sbirlea2019-10-304-307/+2
| | | | | | | | | | | | | | | | Summary: Delete the BasicBlockPass and BasicBlockManager, all its dependencies and update documentation. The BasicBlockManager was improperly tested and found to be potentially broken, and was deprecated as of rL373254. In light of the switch to the new pass manager coming before the next release, this patch is a first cleanup of the LegacyPassManager. Reviewers: chandlerc, echristo Subscribers: mehdi_amini, sanjoy.google, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69121
* [X86] Add FIXME comment to merge more of computeZeroableShuffleElements and ↵Simon Pilgrim2019-10-301-0/+1
| | | | getTargetShuffleAndZeroables
* [X86][SSE] combineX86ShuffleChain - use resolveZeroablesFromTargetShuffle ↵Simon Pilgrim2019-10-301-4/+3
| | | | helper. NFCI.
* [SLP] Vectorize jumbled stores.Alexey Bataev2019-10-301-16/+91
| | | | | | | | | | | | | Summary: Patch adds support for vectorization of the jumbled stores. The value operands are vectorized and then shuffled in the right order before store. Reviewers: RKSimon, spatel, hfinkel, mkuper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D43339
* [NFC] Move this set of STRICT_* cases to be next to the non-strict cases.Kevin P. Neal2019-10-301-10/+10
| | | | Requested by Cameron McInally in D69275.
* [AMDGPU] Simplify VCCZ bug handlingJay Foad2019-10-301-5/+1
| | | | | | | | | | | | | | | | | | | | Summary: VCCZBugHandledSet was used to make sure we don't apply the same workaround more than once to a single cbranch instruction, but it's not necessary because the workaround involves inserting an s_waitcnt instruction, which is enough for subsequent iterations to detect that no further workaround is necessary. Also beef up the test case to check that the workaround was only applied once. I have also manually verified that the test still passes even if I hack the big do-while loop in runOnMachineFunction to run a minimum of five iterations. Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69621
* [NFC][MachineOutliner] Fix typo in commentDavid Tellenbach2019-10-301-1/+1
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* Fix pattern error for S2_tstbit_i instructionIkhlas Ajbar2019-10-301-2/+2
| | | | | It used to generate S2_tstbit_i with constant -33 which resulted in an assert. The reason is log2_32 was called with 64bit value 0.
* [SLPVectorizer] Use getAPInt() for comparison. NFCI.Simon Pilgrim2019-10-301-1/+1
| | | | Technically integers can assert on getZExtValue() if beyond i64 range, and a fuzzer usually find this.....
* [AIX] Lowering CPI/JTI/BA to MIRXiangling Liao2019-10-301-6/+6
| | | | | | Enable lowering of constant pool index, jump table index, and bloack address to MIR on AIX. Differential Revision: https://reviews.llvm.org/D69264
* [AArch64][MachineOutliner] Return address signing for outlined functionsDavid Tellenbach2019-10-301-7/+241
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: During AArch64 frame lowering instructions to enable return address signing are inserted into function if needed. Functions generated during machine outlining don't run through target frame lowering and hence are missing such instructions. This patch introduces the following changes: 1. If not all functions that potentially participate in function outlining agree on their return address signing scope and their return address signing key, outlining is disabled for these functions. 2. If not all functions that potentially participate in function outlining agree on their support for v8.3A features, outlining is disabled for these functions. 2. If all candidate functions agree on the signing scope, signing key and and their support for v8.3 features, the outlined function behaves as if it had the same scope and key attributes and as if it would provide the same v8.3A support as the original functions. Reviewers: olista01, paquette, t.p.northover, ostannard Reviewed By: ostannard Subscribers: ostannard, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69097
* [SelectionDAG] Add support for FP_ROUND in WidenVectorOperand.Jay Foad2019-10-301-4/+14
| | | | | | | | | | | | Summary: This is used on AMDGPU for rounding from v3f64 (which is illegal) to v3f32 (which is legal). Subscribers: jvesely, nhaehnle, tpr, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69339
* [IR] Allow fast math flags on calls with floating point array type.Jay Foad2019-10-302-10/+9
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: This extends the rules for when a call instruction is deemed to be an FPMathOperator, which is based on the type of the call (i.e. the return type of the function being called). Previously we only allowed floating-point and vector-of-floating-point types. Now we also allow arrays (nested to any depth) of floating-point and vector-of-floating-point types. This was motivated by llpc, the pipeline compiler for AMD GPUs (https://github.com/GPUOpen-Drivers/llpc). llpc has many math library functions that operate on vectors, typically represented as <4 x float>, and some that operate on matrices, typically represented as [4 x <4 x float>], and it's useful to be able to decorate calls to all of them with fast math flags. Reviewers: spatel, wristow, arsenm, hfinkel, aemerson, efriedma, cameron.mcinally, mcberg2017, jmolloy Subscribers: wdng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69161
* LiveIntervals: Split live intervals on multiple dead defsKrzysztof Parzyszek2019-10-301-3/+14
| | | | | | | | | | This is a follow-up to D67448. Split live intervals with multiple dead defs during the initial execution of the live interval analysis, but do it outside of the function createAndComputeVirtRegInterval. Differential Revision: https://reviews.llvm.org/D68666
* minidump: Rename some architecture constantsPavel Labath2019-10-301-1/+1
| | | | | | | | | | | | | | | | | | | | | The architecture enum contains two kinds of contstants: the "official" ones defined by Microsoft, and unofficial constants added by breakpad to cover the architectures not described by the first ones. Up until now, there was no big need to differentiate between the two. However, now that Microsoft has defined https://docs.microsoft.com/en-us/windows/win32/api/sysinfoapi/ns-sysinfoapi-system_info a constant for ARM64, we have a name clash. This patch renames all breakpad-defined constants with to include the prefix "BP_". This frees up the name "ARM64", which I'll re-introduce with the new "official" value in a follow-up patch. Reviewers: amccarth, clayborg Subscribers: lldb-commits, llvm-commits Differential Revision: https://reviews.llvm.org/D69285
* [ARM][AArch64][DebugInfo] Improve call site instruction interpretationDjordje Todorovic2019-10-306-9/+105
| | | | | | | | | | | | | Extend the describeLoadedValue() with support for target specific ARM and AArch64 instructions interpretation. The patch provides specialization for ADD and SUB operations that include a register and an immediate/offset operand. Some of the instructions can operate with global string addresses or constant pool indexes but such cases are omitted since we currently lack flexible support for processing such operands at DWARF production stage. Patch by Nikola Prica Differential Revision: https://reviews.llvm.org/D67556
* [AArch64][SVE] Implement masked store intrinsicsKerry McLaughlin2019-10-303-1/+67
| | | | | | | | | | | | | | | | Summary: Adds support for codegen of masked stores, with non-truncating and truncating variants. Reviewers: huntergr, greened, dmgreen, rovka, sdesmalen Reviewed By: dmgreen, sdesmalen Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, cfe-commits, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69378
* [X86] combineOrShiftToFunnelShift - use isOperationLegalOrCustom to check ↵Simon Pilgrim2019-10-301-1/+2
| | | | | | FSHL/FSHR support Remove hard wired legality check.
* [X86] combineOrShiftToFunnelShift - use getShiftAmountTy instead of ↵Simon Pilgrim2019-10-301-5/+8
| | | | hardwiring to MVT::i8
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