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* [AMDGPU] Fix for branch offset hardware workaroundRyan Taylor2019-06-267-24/+111
| | | | | | | | | | | | | | | | | | | Summary: This fixes a hardware bug that makes a branch offset of 0x3f unsafe. This replaces the 32 bit branch with offset 0x3f to a 64 bit instruction that includes the same 32 bit branch and the encoding for a s_nop 0 to follow. The relaxer than modifies the offsets accordingly. Change-Id: I10b7aed99d651f8159401b01bb421f105fa6288e Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63494 llvm-svn: 364451
* Allow matching extend-from-memory with strict FP nodesUlrich Weigand2019-06-261-5/+5
| | | | | | | | | | | | | | | | | | | | | This implements a small enhancement to https://reviews.llvm.org/D55506 Specifically, while we were able to match strict FP nodes for floating-point extend operations with a register as source, this did not work for operations with memory as source. That is because from regular operations, this is represented as a combined "extload" node (which is a variant of a load SD node); but there is no equivalent using a strict FP operation. However, it turns out that even in the absence of an extload node, we can still just match the operations explicitly, e.g. (strict_fpextend (f32 (load node:$ptr)) This patch implements that method to match the LDEB/LXEB/LXDB SystemZ instructions even when the extend uses a strict-FP node. llvm-svn: 364450
* [IndVars] Kill a redundant bit of debug outputPhilip Reames2019-06-261-2/+0
| | | | llvm-svn: 364449
* Fix builbots after r364427.Greg Clayton2019-06-261-1/+1
| | | | | | I was using an iterator that was equal to the end of a collection. llvm-svn: 364447
* [WebAssembly] Omit wrap on i64x2.{shl,shr*} ISel when possibleThomas Lively2019-06-261-2/+8
| | | | | | | | | | | | | | | | | | Summary: Since the WebAssembly SIMD shift instructions take i32 operands, we truncate the i64 operand to <2 x i64> shifts during ISel. When the i64 operand is sign extended from i32, this CL makes it so the sign extension is dropped instead of a wrap instruction added. Reviewers: dschuff, aheejin Subscribers: sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63615 llvm-svn: 364446
* [WebAssembly] Implement tail calls and unify tablegen call classesThomas Lively2019-06-269-151/+186
| | | | | | | | | | | | | | | | | Summary: Implements direct and indirect tail calls enabled by the 'tail-call' feature in both DAG ISel and FastISel. Updates existing call tests and adds new tests including a binary encoding test. Reviewers: aheejin Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62877 llvm-svn: 364445
* Fix leaks in LLVMCreateDisasmCPUFeaturesScott Linder2019-06-262-31/+31
| | | | | | Differential Revision: https://reviews.llvm.org/D63795 llvm-svn: 364444
* [InstCombine] simplify code for inserts -> splat; NFCSanjay Patel2019-06-261-25/+17
| | | | llvm-svn: 364441
* Fix build in shared lib mode.Michael Liao2019-06-262-1/+22
| | | | | | | - The newly added GSYM misses LLVMBuild.txt. Add a barely one to pass the build. llvm-svn: 364440
* [CodeGen] Improve formatting of jump tables (NFC)Evandro Menezes2019-06-261-1/+3
| | | | | | Split jump tables into individual lines and fix spacing. llvm-svn: 364436
* [X86][SSE] X86TargetLowering::isCommutativeBinOp - add PMULDQSimon Pilgrim2019-06-261-3/+1
| | | | | | Allows narrowInsertExtractVectorBinOp to reduce vector size instead of the more restricted SimplifyDemandedVectorEltsForTargetNode llvm-svn: 364434
* [X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQSimon Pilgrim2019-06-261-0/+1
| | | | | | Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
* [X86][SSE] X86TargetLowering::isBinOp - add PCMPGTSimon Pilgrim2019-06-261-0/+1
| | | | | | Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364431
* [X86] shouldScalarizeBinop - never scalarize target opcodes.Simon Pilgrim2019-06-261-2/+9
| | | | | | We have (almost) no target opcodes that have scalar/vector equivalents - for now assume we can't scalarize them (we can add exceptions if we need to). llvm-svn: 364429
* Add GSYM utility files along with unit tests.Greg Clayton2019-06-265-0/+163
| | | | | | | | | | | | | | | | | | | | | | | | The full GSYM patch started with: https://reviews.llvm.org/D53379 In that patch we wanted to split up getting GSYM into the LLVM code base so we are not committing too much code at once. This is a first in a series of patches where I only add the foundation classes along with complete unit tests. They provide the foundation for encoding and decoding a GSYM file. File entries are defined in llvm::gsym::FileEntry. This class splits the file up into a directory and filename represented by uniqued string table offsets. This allows all files that are referred to in a GSYM file to be encoded as 1 based indexes into a global file table in the GSYM file. Function information in stored in llvm::gsym::FunctionInfo. This object represents a contiguous address range that has a name and range with an optional line table and inline call stack information. Line table entries are defined in llvm::gsym::LineEntry. They store only address, file and line information to keep the line tables simple and allows the information to be efficiently encoded in a subsequent patch. Inline information is defined in llvm::gsym::InlineInfo. These structs store the name of the inline function, along with one or more address ranges, and the file and line that called this function. They also contain any child inline information. There are also utility classes for address ranges in llvm::gsym::AddressRange, and string table support in llvm::gsym::StringTable which are simple classes. The unit tests test all the APIs on these simple classes so they will be ready for the next patches where we will create GSYM files and parse GSYM files. Differential Revision: https://reviews.llvm.org/D63104 llvm-svn: 364427
* AMDGPU: Fix unused variableMatt Arsenault2019-06-261-1/+0
| | | | llvm-svn: 364426
* AMDGPU: Check MRI for callee saved regs instead of TRIMatt Arsenault2019-06-264-7/+5
| | | | | | | This should the same, but MRI does allow dynamically changing the CSR set, although currently not used. llvm-svn: 364425
* [InlineCost] cleanup calculations of Cost and ThresholdFedor Sergeev2019-06-261-13/+15
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: Doing better separation of Cost and Threshold. Cost counts the abstract complexity of live instructions, while Threshold is an upper bound of complexity that inlining is comfortable to pay. There are two parts: - huge 15K last-call-to-static bonus is no longer subtracted from Cost but rather is now added to Threshold. That makes much more sense, as the cost of inlining (Cost) is not changed by the fact that internal function is called once. It only changes the likelyhood of this inlining being profitable (Threshold). - bonus for calls proved-to-be-inlinable into callee is no longer subtracted from Cost but added to Threshold instead. While calculations are somewhat different, overall InlineResult should stay the same since Cost >= Threshold compares the same. Reviewers: eraman, greened, chandlerc, yrouban, apilipenko Reviewed By: apilipenko Tags: #llvm Differential Revision: https://reviews.llvm.org/D60740 llvm-svn: 364422
* [X86][Codegen] X86DAGToDAGISel::matchBitExtract(): consistently capture ↵Roman Lebedev2019-06-261-7/+6
| | | | | | lambdas by value llvm-svn: 364420
* [X86] X86DAGToDAGISel::matchBitExtract(): pattern c: truncation awarenessRoman Lebedev2019-06-261-8/+12
| | | | | | | | | | | | | | | | | | | | | | | | Summary: The one thing of note here is that the 'bitwidth' constant (32/64) was previously pessimistic. Given `x & (-1 >> (C - z))`, we were taking `C` to be `bitwidth(x)`, but in reality we want `(-1 >> (C - z))` pattern to mean "low z bits must be all-ones". And for that, `C` should be `bitwidth(-1 >> (C - z))`, i.e. of the shift operation itself. Last pattern D does not seem to exhibit any of these truncation issues. Although it has the opposite problem - if we extract low bits (no shift) from i64, and then truncate to i32, then we fail to shrink this 64-bit extraction into 32-bit extraction. Reviewers: RKSimon, craig.topper, spatel Reviewed By: RKSimon Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62806 llvm-svn: 364419
* [X86] X86DAGToDAGISel::matchBitExtract(): pattern b: truncation awarenessRoman Lebedev2019-06-262-5/+23
| | | | | | | | | | | | | | | | | | Summary: (Not so) boringly identical to pattern a (D62786) Not yet sure how do deal with the last pattern c. Reviewers: RKSimon, craig.topper, spatel Reviewed By: RKSimon Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62793 llvm-svn: 364418
* [X86] X86DAGToDAGISel::matchBitExtract(): pattern a: truncation awarenessRoman Lebedev2019-06-261-18/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Finally tying up loose ends here. The problem is quite simple: If we have pattern `(x >> start) & (1 << nbits) - 1`, and then truncate the result, that truncation will be propagated upwards, into the `and`. And that isn't currently handled. I'm only fixing pattern `a` here, the same fix will be needed for patterns `b`/`c` too. I *think* this isn't missing any extra legality checks, since we only look past truncations. Similary, i don't think we can get any other truncation there other than i64->i32. Reviewers: craig.topper, RKSimon, spatel Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62786 llvm-svn: 364417
* Revert "r364412 [ExpandMemCmp][MergeICmps] Move passes out of CodeGen into ↵Clement Courbet2019-06-268-91/+66
| | | | | | | | | | | | | | opt pipeline." Breaks sanitizers: libFuzzer :: cxxstring.test libFuzzer :: memcmp.test libFuzzer :: recommended-dictionary.test libFuzzer :: strcmp.test libFuzzer :: value-profile-mem.test libFuzzer :: value-profile-strcmp.test llvm-svn: 364416
* [HardwareLoops] NFC - move loop with irreducible control flow checking logic ↵Chen Zheng2019-06-262-8/+15
| | | | | | to HarewareLoopInfo. llvm-svn: 364415
* Fix the build after r364401Hans Wennborg2019-06-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | It was failing with: /b/s/w/ir/cache/builder/src/third_party/llvm/llvm/lib/Target/X86/X86ISelLowering.cpp:18772:66: error: call of overloaded 'makeArrayRef(<brace-enclosed initializer list>)' is ambiguous scaleShuffleMask<int>(Scale, makeArrayRef<int>({ 0, 2, 1, 3 }), Mask); ^ /b/s/w/ir/cache/builder/src/third_party/llvm/llvm/lib/Target/X86/X86ISelLowering.cpp:18772:66: note: candidates are: In file included from /b/s/w/ir/cache/builder/src/third_party/llvm/llvm/include/llvm/CodeGen/MachineFunction.h:20:0, from /b/s/w/ir/cache/builder/src/third_party/llvm/llvm/include/llvm/CodeGen/CallingConvLower.h:19, from /b/s/w/ir/cache/builder/src/third_party/llvm/llvm/lib/Target/X86/X86ISelLowering.h:17, from /b/s/w/ir/cache/builder/src/third_party/llvm/llvm/lib/Target/X86/X86ISelLowering.cpp:14: /b/s/w/ir/cache/builder/src/third_party/llvm/llvm/include/llvm/ADT/ArrayRef.h:480:15: note: llvm::ArrayRef<T> llvm::makeArrayRef(const std::vector<_RealType>&) [with T = int] ArrayRef<T> makeArrayRef(const std::vector<T> &Vec) { ^ /b/s/w/ir/cache/builder/src/third_party/llvm/llvm/include/llvm/ADT/ArrayRef.h:485:37: note: llvm::ArrayRef<T> llvm::makeArrayRef(const llvm::ArrayRef<T>&) [with T = int] template <typename T> ArrayRef<T> makeArrayRef(const ArrayRef<T> &Vec) { ^ llvm-svn: 364414
* [ExpandMemCmp][MergeICmps] Move passes out of CodeGen into opt pipeline.Clement Courbet2019-06-268-66/+91
| | | | | | | | | This allows later passes (in particular InstCombine) to optimize more cases. One that's important to us is `memcmp(p, q, constant) < 0` and memcmp(p, q, constant) > 0. llvm-svn: 364412
* [X86][AVX] combineExtractSubvector - 'little to big' ↵Simon Pilgrim2019-06-261-0/+28
| | | | | | | | extract_subvector(bitcast()) support Ideally this needs to be a generic combine in DAGCombiner::visitEXTRACT_SUBVECTOR but there's some nasty regressions in aarch64 due to neon shuffles not handling bitcasts at all..... llvm-svn: 364407
* [DAGCombine] visitEXTRACT_SUBVECTOR - add TODO for ↵Simon Pilgrim2019-06-261-0/+1
| | | | | | | | extract_subvector(bitcast()) support We support 'big to little' (e.g. extract_subvector(v16i8 bitcast(v2i64))) but not 'little to big' cases (e.g. extract_subvector(v2i64 bitcast(v16i8))) llvm-svn: 364405
* [ARM] Handle fixup_arm_pcrel_9 correctly on big-endian targetsMikhail Maltsev2019-06-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | Summary: The getFixupKindContainerSizeBytes function returns the size of the instruction containing a given fixup. Currently fixup_arm_pcrel_9 is not handled in this function, this causes an assertion failure in the debug build and incorrect codegen in the release build. This patch fixes the problem. Reviewers: ostannard, simon_tatham Reviewed By: ostannard Subscribers: javed.absar, kristof.beyls, hiraditya, pbarrio, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63778 llvm-svn: 364404
* [RISCV] Add pseudo instruction for calls with explicit registerLewis Revill2019-06-264-11/+38
| | | | | | | | | | | | | | This patch adds the PseudoCALLReg instruction which allows using an explicit register operand as the destination for the return address. GCC can successfully parse this form of the call instruction, which would be used for calls to functions which do not use ra as the return address register, such as the __riscv_save libcalls. This patch forms the first part of an implementation of -msave-restore for RISC-V. Differential Revision: https://reviews.llvm.org/D62685 llvm-svn: 364403
* [X86][AVX] truncateVectorWithPACK - avoid bitcasted shufflesSimon Pilgrim2019-06-261-2/+5
| | | | | | | | truncateVectorWithPACK is often used in conjunction with ComputeNumSignBits which struggles when peeking through bitcasts. This fix tries to avoid bitcast(shuffle(bitcast())) patterns in the 256-bit 64-bit sublane shuffles so we can still see through at least until lowering when the shuffles will need to be bitcasted to widen the shuffle type. llvm-svn: 364401
* [LoopUnroll] Add support for loops with exiting headers and uncond latches.Florian Hahn2019-06-261-60/+170
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch generalizes the UnrollLoop utility to support loops that exit from the header instead of the latch. Usually, LoopRotate would take care of must of those cases, but in some cases (e.g. -Oz), LoopRotate does not kick in. Codesize impact looks relatively neutral on ARM64 with -Oz + LTO. Program master patch diff External/S.../CFP2006/447.dealII/447.dealII 629060.00 627676.00 -0.2% External/SPEC/CINT2000/176.gcc/176.gcc 1245916.00 1244932.00 -0.1% MultiSourc...Prolangs-C/simulator/simulator 86100.00 86156.00 0.1% MultiSourc...arks/Rodinia/backprop/backprop 66212.00 66252.00 0.1% MultiSourc...chmarks/Prolangs-C++/life/life 67276.00 67312.00 0.1% MultiSourc...s/Prolangs-C/compiler/compiler 69824.00 69788.00 -0.1% MultiSourc...Prolangs-C/assembler/assembler 86672.00 86696.00 0.0% Reviewers: efriedma, vsk, paquette Reviewed By: paquette Differential Revision: https://reviews.llvm.org/D61962 llvm-svn: 364398
* [HardwareLoops] NFC - move loop with irreducible control flow checking logic ↵Chen Zheng2019-06-262-10/+10
| | | | | | to isHardwareLoopProfitable() llvm-svn: 364397
* [ExpandMemCmp] Honor prefer-vector-width.Clement Courbet2019-06-261-2/+3
| | | | | | | | | | | | Reviewers: gchatelet, echristo, spatel, atdt Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63769 llvm-svn: 364384
* [PowerPC] Fixed missing change flag of emitRLDICWhenLoweringJumpTablesKai Luo2019-06-261-9/+10
| | | | | | | | | PPCMIPeephole::emitRLDICWhenLoweringJumpTables should return a bool value to indicate optimization is conducted or not. Differential Revision: https://reviews.llvm.org/D63801 llvm-svn: 364383
* Teach the DAGCombine to fold this pattern(c1 and c2 is constant).QingShan Zhang2019-06-261-2/+28
| | | | | | | | | | | | | | | | | | // fold (sext (select cond, c1, c2)) -> (select cond, sext c1, sext c2) // fold (zext (select cond, c1, c2)) -> (select cond, zext c1, zext c2) // fold (aext (select cond, c1, c2)) -> (select cond, sext c1, sext c2) Sign extend the operands if it is any_extend, to keep the signess of the operands that, the other combine rule would apply. The any_extend is handled as zero extend for constants. i.e. t1: i8 = select t0, Constant:i8<-1>, Constant:i8<0> t2: i64 = any_extend t1 --> t3: i64 = select t0, Constant:i64<-1>, Constant:i64<0> --> t4: i64 = sign_extend_inreg t3 Differential Revision: https://reviews.llvm.org/D63318 llvm-svn: 364382
* [ARM] Fix -Wimplicit-fallthrough after D60709/r364331Fangrui Song2019-06-261-4/+3
| | | | llvm-svn: 364376
* [PowerPC] Mark FCOPYSIGN legal for FP vectorsNemanja Ivanovic2019-06-261-0/+2
| | | | | | | | | | This was just an omission in the back end. We have had the instructions for both single and double precision for a few HW generations, but never got around to legalizing these. Differential revision: https://reviews.llvm.org/D63634 llvm-svn: 364373
* [PowerPC][NFC] Move peephole optimization of RLDICR into a method.Kai Luo2019-06-261-47/+57
| | | | llvm-svn: 364372
* MC: correct the emission of weak aliases in COFFSaleem Abdulrasool2019-06-261-1/+1
| | | | | | | | | | | The weak alias should have the characteristics set to `IMAGE_EXTERN_WEAK_SEARCH_ALIAS` to indicate that the weak external here is a symbol alias and that the symbol is aliased to a locally defined symbol. We were previously setting the characteristics to `IMAGE_EXTERN_WEAK_SEARCH_LIBRARY` which indicates that the symbol should be looked for in the libraries. llvm-svn: 364370
* [WebAssembly] Fix list of relocations with addends in lldKeno Fischer2019-06-262-13/+15
| | | | | | | | | | | | | Summary: The list of relocations with addend in lld was missing `R_WASM_MEMORY_ADDR_REL_SLEB`, causing `wasm-ld` to generate corrupted output. This fixes that problem and while we're at it pulls the list of such relocations into the Wasm.h header, to avoid duplicating it in multiple places. Reviewers: sbc100 Differential Revision: https://reviews.llvm.org/D63696 llvm-svn: 364367
* [WebAssembly] Remove catch_all from AsmParserHeejin Ahn2019-06-251-4/+0
| | | | | | | | | | | | | | | | | Summary: `catch_all` is from the first version of EH proposal and now has been removed. There were no tests covering this, and thus no tests to remove or fix. Reviewers: aardappel Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63737 llvm-svn: 364360
* Dump what value failed byval attribute verificationReid Kleckner2019-06-251-1/+1
| | | | | | | This verifier check is failing for us while doing ThinLTO on Chrome for x86, see https://crbug.com/978218, and this helps to debug the problem. llvm-svn: 364357
* [MachinePipeliner] Fix risky iterator usage R++, --RJinsong Ji2019-06-251-7/+3
| | | | | | | | | | | | | When we calculate MII, we use two loops, one with iterator R++ to check whether we can reserve the resource, then --R to move back the iterator to do reservation. This is risky, as R++, --R may not point to the same element at all. The can cause wrong MII. Differential Revision: https://reviews.llvm.org/D63536 llvm-svn: 364353
* Don't look for the TargetFrameLowering in the implementationMatt Arsenault2019-06-254-8/+4
| | | | | | The same oddity was apparently copy-pasted between multiple targets. llvm-svn: 364349
* [InstCombine] Simplify icmp ult/uge (shl %x, C2), C1 iff C1 is power of two ↵Huihui Zhang2019-06-251-0/+21
| | | | | | | | | | | | | | | | | | | | | | | -> icmp eq/ne (and %x, (lshr -C1, C2)), 0. Simplify 'shl' inequality test into 'and' equality test. This pattern happens in the middle-end while simplifying bitfield access, Exposed in https://reviews.llvm.org/D63505 https://rise4fun.com/Alive/6uz Reviewers: lebedev.ri, efriedma Reviewed By: lebedev.ri Subscribers: spatel, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63675 llvm-svn: 364348
* [LFTR] Adjust debug output to include extensions (if any)Philip Reames2019-06-251-7/+8
| | | | llvm-svn: 364346
* Update phis in AMDGPUUnifyDivergentExitNodesDiego Novillo2019-06-251-7/+4
| | | | | | | | | | | | | | | Original patch https://reviews.llvm.org/D63659 from Steven Perron <stevenperron@google.com> The pass AMDGPUUnifyDivergentExitNodes does not update the phi nodes in the successors of blocks that is splits. This is fixed by calling BasicBlock::splitBasicBlock to split the block instead of doing it manually. This does extra work because a new conditional branch is created in BB which is immediately replaced, but I think the simplicity is worth it. It also helps make the code more future proof in case other things need to be updated. llvm-svn: 364342
* [InstCombine] reduce checks for power-of-2-or-zero using ctpopSanjay Patel2019-06-251-12/+10
| | | | | | | | | | | | | | | | | | | | | | | This follows up the transform from rL363956 to use the ctpop intrinsic when checking for power-of-2-or-zero. This is matching the isPowerOf2() patterns used in PR42314: https://bugs.llvm.org/show_bug.cgi?id=42314 But there's at least 1 instcombine follow-up needed to match the alternate form: (v & (v - 1)) == 0; We should have all of the backend expansions handled with: rL364319 (x86-specific changes still needed for optimal code based on subtarget) And the larger patterns to exclude zero as a power-of-2 are joining with this change after: rL364153 ( D63660 ) rL364246 Differential Revision: https://reviews.llvm.org/D63777 llvm-svn: 364341
* [AMDGPU] Removed dead SIMachineFunctionInfo::getWorkItemIDVGPR()Stanislav Mekhanoshin2019-06-252-20/+0
| | | | | | Differential Revision: https://reviews.llvm.org/D63780 llvm-svn: 364339
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