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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2019-06-26 14:58:11 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2019-06-26 14:58:11 +0000 |
| commit | 435ee9fb1f86a8f3798c8953b5d1a0b29849fd4e (patch) | |
| tree | 7826188eaa25740e5ec59f57173775cb2caab7b1 /llvm/lib | |
| parent | 3f3eacfec1cccf61ee5444832878d169ad5cc349 (diff) | |
| download | bcm5719-llvm-435ee9fb1f86a8f3798c8953b5d1a0b29849fd4e.tar.gz bcm5719-llvm-435ee9fb1f86a8f3798c8953b5d1a0b29849fd4e.zip | |
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PMULDQ
Allows narrowInsertExtractVectorBinOp to reduce vector size instead of the more restricted SimplifyDemandedVectorEltsForTargetNode
llvm-svn: 364434
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 4eb3323b945..e81339d8eb7 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -28587,6 +28587,7 @@ bool X86TargetLowering::isCommutativeBinOp(unsigned Opcode) const { switch (Opcode) { // TODO: Add more X86ISD opcodes once we have test coverage. case X86ISD::PCMPEQ: + case X86ISD::PMULDQ: case X86ISD::PMULUDQ: case X86ISD::FMAXC: case X86ISD::FMINC: @@ -34007,9 +34008,6 @@ bool X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode( insertSubVector(UndefVec, ExtOp, 0, TLO.DAG, DL, ExtSizeInBits); return TLO.CombineTo(Op, Insert); } - // Arithmetic Ops. - case X86ISD::PMULDQ: - case X86ISD::PMULUDQ: // Target Shuffles. case X86ISD::PSHUFB: case X86ISD::UNPCKL: |
