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* [WebAssembly] Use target-independent saturating addThomas Lively2018-10-252-2/+8
| | | | | | | | | | Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D53721 llvm-svn: 345299
* [FPEnv] Last BinaryOperator::isFNeg(...) to m_FNeg(...) changesCameron McInally2018-10-252-7/+11
| | | | | | | | | Replacing BinaryOperator::isFNeg(...) to avoid regressions when we separate FNeg from the FSub IR instruction. Differential Revision: https://reviews.llvm.org/D53650 llvm-svn: 345295
* [GlobalISel] LegalizerHelper: Fix the incorrect alignment when splitting ↵Volkan Keles2018-10-251-6/+6
| | | | | | | | | | | | | | loads/stores in narrowScalar Reviewers: dsanders, bogner, jpaquette, aemerson, ab, paquette Reviewed By: dsanders Subscribers: rovka, kristof.beyls, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D53664 llvm-svn: 345292
* [LegalizeDAG] Remove dead SINT_TO_FP legalization codeSimon Pilgrim2018-10-251-54/+19
| | | | | | | | As noticed on D52965, the SINT_TO_FP i64 to f32 legalization code has been dead for years - protected by an assert. Differential Revision: https://reviews.llvm.org/D53703 llvm-svn: 345290
* [GISel] LegalizerInfo: Rename MemDesc::Size to SizeInBits to make the value ↵Volkan Keles2018-10-253-5/+5
| | | | | | | | clearer Requested in D53679. llvm-svn: 345288
* [X86] Remove ProcIntelKNL and replace with a SlowPMADDWD flag to use in the ↵Craig Topper2018-10-253-8/+12
| | | | | | one place it was checked. llvm-svn: 345286
* [X86] Remove some uarch tuning flags from KNL that look to have been ↵Craig Topper2018-10-251-4/+0
| | | | | | | | | | inherited from SNB/IVB incorrectly KNL is based on a modified Silvermont core so I don't think these features apply. I think the LEA flag is probably also wrong, but I'm less sure as I barely understand the 3 LEA flags we have currently. Differential Revision: https://reviews.llvm.org/D53671 llvm-svn: 345285
* [AArch64][GlobalISel] Fix the LegalityPredicate for lowerIf for G_LOAD/G_STOREVolkan Keles2018-10-251-2/+2
| | | | | | | | | | | | | | | | | | | Summary: Currently, Legalizer is trying to lower G_LOAD with a vector type that has more than two elements due to the incorrect LegalityPredicate. This patch fixes the issue by removing the multiplication by 8 as `MemDesc.Size` already contains the size in bits. Reviewers: dsanders, aemerson Reviewed By: dsanders Subscribers: rovka, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D53679 llvm-svn: 345282
* [AArch64] Refactor Exynos feature sets (NFC)Evandro Menezes2018-10-251-12/+6
| | | | llvm-svn: 345279
* [AArch64] Add EXT patterns for 64-bit EXT of a subvector of a 128-bit vectorJohn Brawn2018-10-251-0/+19
| | | | | | | | | | If we have a 64-bit EXT where one of the operands is a subvector of a 128-bit vector then in some cases we can eliminate an extract_subvector by converting to a 128-bit EXT of the 128-bit vector. Differential Revision: https://reviews.llvm.org/D53582 llvm-svn: 345275
* [ARM] Use Cortex-A57 sched model for Cortex-A72Sam Parker2018-10-251-1/+1
| | | | | | | | | | | This mirrors what we already do for AArch64 as the cores are similar. As discussed in the review, enabling the machine scheduler causes more variations in performance changes so it is not enabled for now. This patch improves LNT scores by a geomean of 1.57% at -O3. Differential Revision: https://reviews.llvm.org/D53562 llvm-svn: 345272
* [AArch64] Refactor definition of EXT patterns to use a multiclassJohn Brawn2018-10-251-38/+18
| | | | | | | | | | Using a multiclass reduces duplication, and makes it easier to add new patterns later. This refactoring does add some new patterns, but as far as I can tell there's no IR that will end up triggering them so this is effectively NFC. Differential Revision: https://reviews.llvm.org/D53580 llvm-svn: 345271
* [AArch64] Do 64-bit vector move of 0 and -1 by extracting from the 128-bit moveJohn Brawn2018-10-251-10/+12
| | | | | | | | | | Currently a vector move of 0 or -1 will use different instructions depending on the size of the vector. Using a single instruction (the 128-bit one) for both gives more opportunity for Machine CSE to eliminate instructions. Differential Revision: https://reviews.llvm.org/D53579 llvm-svn: 345270
* [DEBUG_INFO][NVPTX]Fix processing of DBG_VALUES.Alexey Bataev2018-10-251-0/+19
| | | | | | | | | | | | | | | | | Summary: If the instruction in the eliminateFrameIndex function is a DBG_VALUE instruction, it requires special processing. The frame register is set to VRFrame and the offset is based on the object offset. The code is similar to the code used in lib/CodeGen/PrologEpilogInserter.cpp. Reviewers: tra Subscribers: jholewinski, llvm-commits Differential Revision: https://reviews.llvm.org/D53657 llvm-svn: 345269
* [GlobalISel] Use the target preferred type for G_EXTRACT_VECTOR_ELT index.Amara Emerson2018-10-253-1/+33
| | | | | | Allows for better imported pattern re-use. llvm-svn: 345265
* IR: Optimize StructType::get to perform one hash lookup instead of two, NFCIKrasimir Georgiev2018-10-251-7/+14
| | | | | | | | | | | | | | | | | Summary: This function was performing two hash lookups when a new struct type was requested: first checking if it exists and second to insert it. This patch updates the function to perform a single hash lookup in this case by updating the value in the hash table in-place in case the struct type was not there before. Similar to r345151. Reviewers: bkramer Reviewed By: bkramer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53689 llvm-svn: 345264
* [CostModel][X86] Add realistic vXi64 uitofp vXf64 costsSimon Pilgrim2018-10-251-7/+6
| | | | | | Match codegen improvements from D53649/rL345256 llvm-svn: 345263
* [RISCV] Use PatFrags for variable shift patternsAlex Bradbury2018-10-251-10/+9
| | | | | | This follows SystemZ and I think is cleaner vs the multiclass. llvm-svn: 345262
* [CostModel][X86] Add realistic i64 uitofp f64 scalar costsSimon Pilgrim2018-10-251-0/+5
| | | | llvm-svn: 345261
* Missing semicolon.Simon Pilgrim2018-10-251-1/+1
| | | | llvm-svn: 345257
* [TargetLowering] Improve vXi64 UINT_TO_FP vXf64 support (P38226)Simon Pilgrim2018-10-253-25/+53
| | | | | | | | | | | | As suggested on D52965, this patch moves the i64 to f64 UINT_TO_FP expansion code from LegalizeDAG into TargetLowering and makes it available to LegalizeVectorOps as well. Not only does this help perform X86 lowering as a true vectorization instead of (partially vectorized) scalar conversions, it avoids the HADDPD op from the scalar code which can be slow on most targets. The AVX512F does have the vcvtusi2sdq scalar operation but we don't unroll to use it as it seems to only help for the v2f64 case - otherwise the unrolling cost will certainly be too high. My feeling is that we should leave it to the vectorizers - and if it generates the vector UINT_TO_FP we should use it. Differential Revision: https://reviews.llvm.org/D53649 llvm-svn: 345256
* [llvm-dwarfdump] - Fix incorrect parsing of the DW_LLE_startx_lengthGeorge Rimar2018-10-253-8/+25
| | | | | | | | | | | | | | | | | As was already mentioned in comments for D53364, DWARF 5 spec says about DW_LLE_startx_length: "This is a form of bounded location description that has two unsigned ULEB operands. The first value is an address index (into the .debug_addr section) that indicates the beginning of the address range over which the location is valid. The second value is the length of the range. ") Currently, the length is always parsed as U32. Patch change the behavior to parse DW_LLE_startx_length as ULEB128 for DWARF 5 and keeps it as U32 for DWARF4+(pre-DWARF5) for compatibility. Differential revision: https://reviews.llvm.org/D53564 llvm-svn: 345254
* [TTI] Add generic SK_Broadcast shuffle costsSimon Pilgrim2018-10-252-5/+35
| | | | | | | | | | I noticed while fixing PR39368 that we don't have generic shuffle costs for broadcast style shuffles. This patch adds SK_BROADCAST handling, but exposes ARM/AARCH64 lack of handling of this type, which I've added a fix for at the same time. Differential Revision: https://reviews.llvm.org/D53570 llvm-svn: 345253
* [DebugInfo][Dexter] Unreachable line stepped onto after SimplifyCFG.Carlos Alberto Enciso2018-10-252-18/+45
| | | | | | | | When SimplifyCFG changes the PHI node into a select instruction, the debug line records becomes ambiguous. It causes the debugger to display unreachable source lines. Differential Revision: https://reviews.llvm.org/D53287 llvm-svn: 345250
* Add -instcombine-code-sinking optionGabor Buella2018-10-251-1/+5
| | | | | | | | | | Reviewers: craig.topper, andrew.w.kaylor, efriedma Reviewed By: craig.topper, andrew.w.kaylor, efriedma Differential Revision: https://reviews.llvm.org/D52709 llvm-svn: 345248
* [MCSched] Bind PFM Counters to the CPUs instead of the SchedModel.Clement Courbet2018-10-252-59/+79
| | | | | | | | | | | | | | | | Summary: The pfm counters are now in the ExegesisTarget rather than the MCSchedModel (PR39165). This also compresses the pfm counter tables (PR37068). Reviewers: RKSimon, gchatelet Subscribers: mgrang, llvm-commits Differential Revision: https://reviews.llvm.org/D52932 llvm-svn: 345243
* [X86] Don't use the OriginalDemandedBits to calculate the DemandedMask for ↵Craig Topper2018-10-251-1/+2
| | | | | | | | | | PMULUDQ/PMULDQ inputs. Multiply a is complex operation so just because some bit of the output isn't used doesn't mean that bit of the input isn't used. We might able to bound it, but it will require some more thought. llvm-svn: 345241
* [X86] Fix typo in comment. NFCCraig Topper2018-10-251-1/+1
| | | | llvm-svn: 345236
* [WebAssembly] Set LoadExt and TruncStore actions for SIMD typesThomas Lively2018-10-251-0/+13
| | | | | | | | | | | | Summary: Fixes part of the problem reported in bug 39275. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits, alexcrichton Differential Revision: https://reviews.llvm.org/D53542 llvm-svn: 345230
* DebugInfo: Reuse common addresses for rnglist base address selectionsDavid Blaikie2018-10-243-0/+15
| | | | | | | | | | | | | | | | | | This makes the offsets larger (since they are further from the base address) but those are in the .dwo - and allows removing addresses and relocations from the .o file. This could be built into the AddressPool more fundamentally, perhaps - when you ask for an AddressPool entry you could say "or give me some other entry and an offset I need to use" - though what to do about situations where the first use of an address in a section is not the earliest address in that section... is tricky. At least with range addresses we can be fairly sure we've seen the earliest address first because we see the start address for the function. llvm-svn: 345224
* [WebAssembly] Fix immediate of rethrow when throwing to callerHeejin Ahn2018-10-241-1/+1
| | | | | | | | | | | | | | | | | | Summary: Currently when assigning depths 'rethrow' does not take the whole control flow stack into accounts but only considers EH pad stacks. When assigning depth immmediates to rethrows, in normal cases it is done correctly but when a rethrow instruction throws up to a caller, i.e., we convert a pseudo RETHROW_TO_CALLER instruction to a rethrow, it mistakenly compute the whole stack depth. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D53619 llvm-svn: 345223
* [WebAssembly] Retain shuffle types during custom loweringThomas Lively2018-10-242-4/+4
| | | | | | | | | | | | | | | Summary: Changing the node type in lowering was violating assumptions made in the DAG combiner, so don't change the node type any more. This fixes one of the issues reported in bug 39275. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits, alexcrichton Differential Revision: https://reviews.llvm.org/D53537 llvm-svn: 345221
* [ELF] Fix large code model MIR verifier errorsReid Kleckner2018-10-243-46/+22
| | | | | | | | | | | Instead of using the MOVGOT64r pseudo, use the existing MO_PIC_BASE_OFFSET support on symbol operands. Now I don't have to create a "scratch register operand" for the pseudo to use, and the register allocator can make better decisions. Fixes some X86 verifier errors tracked in PR27481. llvm-svn: 345219
* [NFC] Rename minnan and maxnan to minimum and maximumThomas Lively2018-10-2419-104/+102
| | | | | | | | | | | | | | | Summary: Changes all uses of minnan/maxnan to minimum/maximum globally. These names emphasize that the semantic difference between these operations is more than just NaN-propagation. Reviewers: arsenm, aheejin, dschuff, javed.absar Subscribers: jholewinski, sdardis, wdng, sbc100, jgravelle-google, jrtc27, atanasyan, llvm-commits Differential Revision: https://reviews.llvm.org/D53112 llvm-svn: 345218
* Update MemorySSA in LoopRotate.Alina Sbirlea2018-10-242-13/+75
| | | | | | | | | | | | Summary: Teach LoopRotate to preserve MemorySSA. Enable tests for correctness, dependency disabled by default. Subscribers: sanjoy, jlebar, Prazek, george.burgess.iv, llvm-commits Differential Revision: https://reviews.llvm.org/D51718 llvm-svn: 345216
* llvm-dwarfdump: Account for skeleton addr_base when dumping addresses in ↵David Blaikie2018-10-241-0/+10
| | | | | | split unit in the same file llvm-svn: 345215
* [VFS] Remove 'ignore-non-existent-contents' attribute for YAML-based VFS.Volodymyr Sapsai2018-10-241-22/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | 'ignore-non-existent-contents' stopped working after r342232 in a way that the actual attribute value isn't used and it works as if it is always `true`. Common use case for VFS iteration is iterating through files in umbrella directories for modules. Ability to detect if some VFS entries point to non-existing files is nice but non-critical. Instead of adding back support for `'ignore-non-existent-contents': false` I am removing the attribute, because such scenario isn't used widely enough and stricter checks don't provide enough value to justify the maintenance. Change is done both in LLVM and Clang, corresponding Clang commit is r345212. rdar://problem/45176119 Reviewers: bruno Reviewed By: bruno Subscribers: hiraditya, dexonsmith, sammccall, cfe-commits Differential Revision: https://reviews.llvm.org/D53228 llvm-svn: 345213
* [SelectionDAG] DAG combiner for fminnan and fmaxnanThomas Lively2018-10-241-20/+20
| | | | | | | | | | | | Summary: Depends on D52765. Reviewers: aheejin, dschuff Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D52768 llvm-svn: 345210
* [HotColdSplitting] Identify larger cold regions using domtree queriesVedant Kumar2018-10-242-201/+192
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current splitting algorithm works in three stages: 1) Identify cold blocks, then 2) Use forward/backward propagation to mark hot blocks, then 3) Grow a SESE region of blocks *outside* of the set of hot blocks and start outlining. While testing this pass on Apple internal frameworks I noticed that some kinds of control flow (e.g. loops) are never outlined, even though they unconditionally lead to / follow cold blocks. I noticed two other issues related to how cold regions are identified: - An inconsistency can arise in the internal state of the hotness propagation stage, as a block may end up in both the ColdBlocks set and the HotBlocks set. Further inconsistencies can arise as these sets do not match what's in ProfileSummaryInfo. - It isn't necessary to limit outlining to single-exit regions. This patch teaches the splitting algorithm to identify maximal cold regions and outline them. A maximal cold region is defined as the set of blocks post-dominated by a cold sink block, or dominated by that sink block. This approach can successfully outline loops in the cold path. As a side benefit, it maintains less internal state than the current approach. Due to a limitation in CodeExtractor, blocks within the maximal cold region which aren't dominated by a single entry point (a so-called "max ancestor") are filtered out. Results: - X86 (LNT + -Os + externals): 134KB of TEXT were outlined compared to 47KB pre-patch, or a ~3x improvement. Did not see a performance impact across two runs. - AArch64 (LNT + -Os + externals + Apple-internal benchmarks): 149KB of TEXT were outlined. Ditto re: performance impact. - Outlining results improve marginally in the internal frameworks I tested. Follow-ups: - Outline more than once per function, outline large single basic blocks, & try to remove unconditional branches in outlined functions. Differential Revision: https://reviews.llvm.org/D53627 llvm-svn: 345209
* [SourceMgr][FileCheck] Obey -color by extending WithColorJoel E. Denny2018-10-242-79/+92
| | | | | | | | | | | | | | | | | | | | | | | | | (Relands r344930, reverted in r344935, and now hopefully fixed for Windows.) While this change specifically targets FileCheck, it affects any tool using the same SourceMgr facilities. Previously, -color was documented in FileCheck's -help output, but -color had no effect. Now, -color obeys its documentation: it forces colors to be used in FileCheck diagnostics even when stderr is not a terminal. -color is especially helpful when combined with FileCheck's -v, which can produce a long series of diagnostics that you might wish to pipe to a pager, such as less -R. The WithColor extensions here will also help to clean up color usage in FileCheck's annotated dump of input, which is proposed in D52999. Reviewed By: JDevlieghere, zturner Differential Revision: https://reviews.llvm.org/D53419 llvm-svn: 345202
* [AArch64] Refactor Exynos machine modelEvandro Menezes2018-10-244-70/+86
| | | | | | Effectively, NFC. llvm-svn: 345201
* [DAG] check more operands for cycles when merging stores.Tim Northover2018-10-241-8/+8
| | | | | | | | | | | | | | | | | Until now, we've only checked whether merging stores would cause a cycle via the value argument, but the address and indexed offset arguments are also capable of creating cycles in some situations. The addresses are all base+offset with notionally the same base, but the base SDNode may still be different (e.g. via an indexed load in one case, and an ISD::ADD elsewhere). This allows cycles to creep in if one of these sources depends on another. The indexed offset is usually undef (representing a non-indexed store), but on some architectures (e.g. 32-bit ARM-mode ARM) it can be an arbitrary value, again allowing dependency cycles to creep in. llvm-svn: 345200
* [X86] Add *SP to tailcall register class to fix verifier errorReid Kleckner2018-10-241-3/+4
| | | | | | | | | It's possible to do a tail call to a stack argument. LLVM already calculates the right stack offset to call through. Fixes the sibcall* and musttail* verifier failures tracked at PR27481. llvm-svn: 345197
* [MIR] Add hasWinCFI fieldSanjin Sijaric2018-10-242-0/+2
| | | | | | | | | Adding hasWinCFI field so that I can add MIR test cases to https://reviews.llvm.org/D50166. Differential Revision: https://reviews.llvm.org/D51201 llvm-svn: 345196
* [MC] Separate masm integer literal lexer support from inline asmReid Kleckner2018-10-244-21/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This renames the IsParsingMSInlineAsm member variable of AsmLexer to LexMasmIntegers and moves it up to MCAsmLexer. This is the only behavior controlled by that variable. I added a public setter, so that it can be set from outside or from the llvm-mc command line. We may need to arrange things so that users can get this behavior from clang, but that's future work. I also put additional hex literal lexing functionality under this flag to fix PR32973. It appears that this hex literal parsing wasn't intended to be enabled in non-masm-style blocks. Now, masm integers (0b1101 and 0ABCh) work in __asm blocks from clang, but 0b label references work when using .intel_syntax in standalone .s files. However, 0b label references will *not* work from __asm blocks in clang. They will work from GCC inline asm blocks, which it sounds like is important for Crypto++ as mentioned in PR36144. Essentially, we only lex masm literals for inline asm blobs that use intel syntax. If the .intel_syntax directive is used inside a gnu-style inline asm statement, masm literals will not be lexed, which is compatible with gas and llvm-mc standalone .s assembly. This fixes PR36144 and PR32973. Reviewers: Gerolf, avt77 Subscribers: eraman, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D53535 llvm-svn: 345189
* AArch64: add a pass to compress jump-table entries when possible.Tim Northover2018-10-2412-4/+384
| | | | llvm-svn: 345188
* [AArch64] Refactor Exynos machine model (NFC)Evandro Menezes2018-10-244-42/+42
| | | | llvm-svn: 345187
* [AArch64] Fix overlapping instructionsEvandro Menezes2018-10-241-5/+1
| | | | | | | Fix overlapping instruction descriptions in the machine model for Exynos M3. Effectively, NFC. llvm-svn: 345186
* [X86] Explicitly list all KNL features of inheriting from IVB. NFCCraig Topper2018-10-241-1/+23
| | | | | | I'm not sure all the microarchitectural tuning flags that have been added to IVBFeatures are relevant for KNL. Separating will allow us to see and audit them. There might even be some simplification opportunities in the Sandy Bridge through Icelake inheritance line without KNL using the same chain. llvm-svn: 345183
* [X86][SSE] Add SimplifyDemandedBitsForTargetNode PMULDQ/PMULUDQ handlingSimon Pilgrim2018-10-242-6/+32
| | | | | | | | | | Add X86 SimplifyDemandedBitsForTargetNode and use it to simplify PMULDQ/PMULUDQ target nodes. This enables us to repeatedly simplify the node's arguments after the previous approach had to be reverted due to PR39398. Differential Revision: https://reviews.llvm.org/D53643 llvm-svn: 345182
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