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| author | Sam Parker <sam.parker@arm.com> | 2018-10-25 15:08:29 +0000 |
|---|---|---|
| committer | Sam Parker <sam.parker@arm.com> | 2018-10-25 15:08:29 +0000 |
| commit | a16667e79be9164943dd76235d5406ae519b9042 (patch) | |
| tree | 8433d048538fa26cffe855bc4b73087c427f1fc9 /llvm/lib | |
| parent | b8e7887f33290b48918bc2dd1640cbeb69c42ef8 (diff) | |
| download | bcm5719-llvm-a16667e79be9164943dd76235d5406ae519b9042.tar.gz bcm5719-llvm-a16667e79be9164943dd76235d5406ae519b9042.zip | |
[ARM] Use Cortex-A57 sched model for Cortex-A72
This mirrors what we already do for AArch64 as the cores are similar.
As discussed in the review, enabling the machine scheduler causes
more variations in performance changes so it is not enabled for now.
This patch improves LNT scores by a geomean of 1.57% at -O3.
Differential Revision: https://reviews.llvm.org/D53562
llvm-svn: 345272
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARM.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td index fc23495ebf3..b71a09828bc 100644 --- a/llvm/lib/Target/ARM/ARM.td +++ b/llvm/lib/Target/ARM/ARM.td @@ -1043,7 +1043,7 @@ def : ProcessorModel<"cortex-a57", CortexA57Model, [ARMv8a, ProcA57, FeatureAvoidPartialCPSR, FeatureCheapPredicableCPSR]>; -def : ProcNoItin<"cortex-a72", [ARMv8a, ProcA72, +def : ProcessorModel<"cortex-a72", CortexA57Model, [ARMv8a, ProcA72, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, |
