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* Sink DwarfDebug::constructLexicalScopeDIE into DwarfCompileUnitDavid Blaikie2014-10-094-23/+21
| | | | llvm-svn: 219414
* Missing reformattingDavid Blaikie2014-10-091-1/+1
| | | | llvm-svn: 219413
* Sink DwarfDebug::constructInlinedScopeDIE into DwarfCompileUnitDavid Blaikie2014-10-094-44/+50
| | | | | | | | | | | This introduces access to the AbstractSPDies map from DwarfDebug so DwarfCompileUnit can access it. Eventually this'll sink down to DwarfFile, but it'll still be generically accessible - not much encapsulation to provide it. (constructInlinedScopeDIE could stay further up, in DwarfFile to avoid exposing this - but I don't think that's particularly better) llvm-svn: 219411
* [InstCombine] Fix wrong folding of constant comparisons involving ashr and ↵Andrea Di Biagio2014-10-091-1/+2
| | | | | | | | | | | | | | negative values. This patch fixes a bug in method InstCombiner::FoldCmpCstShrCst where we wrongly computed the distance between the highest bits set of two negative values. This fixes PR21222. Differential Revision: http://reviews.llvm.org/D5700 llvm-svn: 219406
* [AArch64] Enable partial & runtime unrolling on cortex-a57.Kevin Qin2014-10-092-0/+14
| | | | llvm-svn: 219401
* Object, COFF: Move the VirtualSize/SizeOfRawData logic to getSectionSizeDavid Majnemer2014-10-091-18/+23
| | | | | | | | While getSectionContents was updated to do the right thing, getSectionSize wasn't. Move the logic to getSectionSize and leverage it from getSectionContents. llvm-svn: 219391
* [AVX512] Extended avx512_binop_rm for AVX512VL subsets.Robert Khasanov2014-10-091-53/+76
| | | | | | | Added avx512_binop_rm_vl multiclass for VL subset Added encoding tests llvm-svn: 219390
* Object, COFF: Cap the section contents to min(VirtualSize, SizeOfRawData)David Majnemer2014-10-091-5/+19
| | | | | | | | | | | | | | | | It is not useful to return the data beyond VirtualSize it's less than SizeOfRawData. An implementation detail of COFF requires the section size to be rounded up to a multiple of FileAlignment; this means that SizeOfRawData is not representative of how large the section is. Instead, we should cap it to VirtualSize when this occurs as it represents the true size of the section. Note that this is only relevant in executable files because this rounding doesn't occur in object files (and VirtualSize is always zero). llvm-svn: 219388
* Remove more calls to getSubtargetImpl from the schedulers andEric Christopher2014-10-093-24/+17
| | | | | | remove cached or unnecessary TargetMachines. llvm-svn: 219387
* Use triple's isiOS() and isOSDarwin() methods.Bob Wilson2014-10-094-6/+5
| | | | | | | These methods are already used in lots of places. This makes things more consistent. NFC. llvm-svn: 219386
* Object: Add range iterators for COFF import/export tableRui Ueyama2014-10-091-0/+26
| | | | llvm-svn: 219383
* Remove unused argument to CreateTargetScheduleState and changeEric Christopher2014-10-097-20/+16
| | | | | | | the TargetMachine to a TargetSubtargetInfo since everything we wanted is off of that. llvm-svn: 219382
* Remove uses of getSubtargetImpl from ResourcePriorityQueue andEric Christopher2014-10-091-7/+5
| | | | | | replace them with calls off of the MachineFuncton. llvm-svn: 219381
* Remove the uses of getSubtargetImpl from InstrEmitter and removeEric Christopher2014-10-092-9/+6
| | | | | | the now unused TargetMachine variable. llvm-svn: 219379
* Use the subtarget on the dag to get TargetFrameLowering ratherEric Christopher2014-10-092-2/+2
| | | | | | than off the target machine. llvm-svn: 219378
* Remove uses of the TargetMachine from FunctionLoweringInfoEric Christopher2014-10-092-15/+11
| | | | | | via caching TargetLowering and using the MachineFunction. llvm-svn: 219375
* Push DwarfDebug::attachRangesOrLowHighPC down into DwarfCompileUnitDavid Blaikie2014-10-094-15/+15
| | | | llvm-svn: 219372
* Sink DwarfDebug::addScopeRangeList down into DwarfCompileUnitDavid Blaikie2014-10-094-37/+43
| | | | | | | | | | | | | (& add a few accessors/make a couple of things public for this - it's a bit of a toss-up, but I think I prefer it this way, keeping some more of the meaty code down in DwarfCompileUnit - if only to make for smaller implementation files, etc) I think we could simplify range handling a bit if we removed the range lists from each unit and just put a single range list on DwarfDebug, similar to address pooling. llvm-svn: 219370
* Remove unnecessary include.Eric Christopher2014-10-081-1/+0
| | | | llvm-svn: 219368
* Use both the cached TLI and the subtarget off of the DAG inEric Christopher2014-10-081-15/+10
| | | | | | the DAG combiner. llvm-svn: 219367
* Remove getSubtargetImpl calls from FastISel, we can get it fromEric Christopher2014-10-081-6/+5
| | | | | | the MachineFunction where it's already cached. llvm-svn: 219366
* Sink DwarfUnit::addSectionDelta into DwarfCompileUnit, the only place it's ↵David Blaikie2014-10-084-14/+12
| | | | | | needed. llvm-svn: 219364
* [AVX512] Rename AVX512_masking* to AVX512_maskable*Adam Nemet2014-10-081-69/+69
| | | | | | | | | | | | | | | | No functional change. This is the current AVX512_maskable multiclass hierarchy: maskable_custom / \ / \ maskable_common maskable_in_asm / \ / \ maskable maskable_3src llvm-svn: 219363
* [AVX512] Intrinsics for vextract*x4Adam Nemet2014-10-081-0/+23
| | | | | | | | This adds the Pat<>'s for the intrinsics. These are necessary because we don't lower these intrinsics to SDNodes but match them directly. See the rational in the previous commit. llvm-svn: 219362
* [AVX512] Add asm-only support for vextract*x4 masking variantsAdam Nemet2014-10-081-7/+19
| | | | | | | | | | | | | | | | These derive from the new asm-only masking definitions. Unfortunately I wasn't able to find a ISel pattern that we could legally generate for the masking variants. The problem is that since the destination is v4* we would need VK4 register classes and v4i1 value types to express the masking. These are however not legal types/classes in AVX512f but only in VL, so things get complicated pretty quickly. We can revisit this question later if we have a more pressing need to express something like this. So the ISel patterns are empty for the masking instructions and the next patch will add Pat<>s instead to match the intrinsics calls with instructions. llvm-svn: 219361
* [AVX512] Move DAG for all-zero node to X86VectorVTInfoAdam Nemet2014-10-081-3/+6
| | | | | | | | | | No functional change. No change in X86.td.expanded except for the appearance of the new attributes. The new attributes will be used in the subsequent patch. llvm-svn: 219360
* [AVX512] Peel off an asm-only class from AVX512_masking_common.Adam Nemet2014-10-081-10/+32
| | | | | | | | | No functional change. This enables the generation of masking instructions that don't provide a ISel pattern. llvm-svn: 219358
* [X86] Don't transform atomic-load-add into an inc/dec when inc/dec is slowRobin Morisset2014-10-081-3/+4
| | | | llvm-svn: 219357
* Reformat some stuff I missed in recent previous commitsDavid Blaikie2014-10-081-2/+4
| | | | llvm-svn: 219356
* Revert r219354. It seems to break some buildbots.Alexey Samsonov2014-10-081-139/+1
| | | | llvm-svn: 219355
* Use llvm-symbolizer to symbolize LLVM/Clang crash dumps.Alexey Samsonov2014-10-081-1/+139
| | | | | | | | | | | | | | | | This change modifies fatal signal handler used in LLVM tools. Now it attempts to find llvm-symbolizer binary and communicates with it in order to turn instruction addresses into function/file/line info entries. This should significantly improve stack traces readability in Debug builds. This feature only works on selected platforms (including Darwin and Linux). If the symbolization fails for some reason, signal handler will fallback to the original behavior. Reviewed in http://reviews.llvm.org/D5610 llvm-svn: 219354
* Sink and coalesce DwarfDebug.cpp::addSectionLabel and ↵David Blaikie2014-10-085-40/+29
| | | | | | DwarfUnit::addSectionLabel down into DwarfCompileUnit::addSectionLabel llvm-svn: 219351
* Remove dead call to getTypeToTransformTo. The result isEric Christopher2014-10-081-3/+1
| | | | | | unused. llvm-svn: 219347
* DebugInfo: The rest of pushing DwarfDebug::constructScopeDIE down into ↵David Blaikie2014-10-082-71/+1
| | | | | | | | | DwarfCompileUnit Funnily enough, I copied it, but didn't actually remove the original in r219345. Let's do that. llvm-svn: 219346
* Push DwarfDebug::constructScopeDIE down into DwarfCompileUnitDavid Blaikie2014-10-083-18/+90
| | | | | | | | | | One of many steps to generalize subprogram emission to both the DWO and non-DWO sections (to emit -gmlt-like data under fission). Once the functions are pushed down into DwarfCompileUnit some of the data structures will be pushed at least into DwarfFile so that they can be unique per-file, allowing emission to both files independently. llvm-svn: 219345
* Remove a bunch of getSubtargetImpl calls since we already haveEric Christopher2014-10-081-35/+6
| | | | | | a cached TLI instance. llvm-svn: 219342
* [X86] Avoid generating inc/dec when slow for x.atomic_store(1 + x.atomic_load())Robin Morisset2014-10-081-2/+2
| | | | | | | | | | | | | | | | | Summary: I had forgotten to check for NotSlowIncDec in the patterns that can generate inc/dec for the above pattern (added in D4796). This currently applies to Atom Silvermont, KNL and SKX. Test Plan: New checks on atomic_mi.ll Reviewers: jfb, nadav Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5677 llvm-svn: 219336
* Inliner: Non-local functions in COMDATs shouldn't be droppedDavid Majnemer2014-10-081-0/+7
| | | | | | | | | | A function with discardable linkage cannot be discarded if its a member of a COMDAT group without considering all the other COMDAT members as well. This sort of thing is already handled by GlobalOpt/GlobalDCE. This fixes PR21206. llvm-svn: 219335
* Fix COFF section index relocation should be 16 bits, not 32Timur Iskhodzhanov2014-10-082-1/+3
| | | | | | | Original patch by Andrey Guskov! http://reviews.llvm.org/D5651 llvm-svn: 219327
* Correctly compute the size of common symbols in COFF.Rafael Espindola2014-10-081-4/+9
| | | | llvm-svn: 219324
* Revert "[InstCombine] re-commit r218721 with fix for pr21199"Justin Bogner2014-10-083-147/+8
| | | | | | | | | | | | | This seems to cause a miscompile when building clang, which causes a bootstrapped clang to fail or crash in several of its tests. See: http://lab.llvm.org:8013/builders/clang-x86_64-darwin11-RA/builds/1184 http://bb.pgr.jp/builders/clang-3stage-x86_64-linux/builds/7813 This reverts commit r219282. llvm-svn: 219317
* [AVX512] Added intrinsics for 128-, 256- and 512-bit versions of ↵Robert Khasanov2014-10-082-6/+38
| | | | | | | | | | | VPCMP/VPCMPU{BWDQ} Added CMP_MASK_CC intrinsic type. Added tests for intrinsics. Patch by Sergey Lisitsyn <sergey.lisitsyn@intel.com> llvm-svn: 219316
* Remove bogus std::error_code returns form SectionRef.Rafael Espindola2014-10-0810-208/+102
| | | | | | | | | | | | | | There are two methods in SectionRef that can fail: * getName: The index into the string table can be invalid. * getContents: The section might point to invalid contents. Every other method will always succeed and returning and std::error_code just complicates the code. For example, a section can have an invalid alignment, but if we are able to get to the section structure at all and create a SectionRef, we will always be able to read that invalid alignment. llvm-svn: 219314
* Fix indentation.Rafael Espindola2014-10-081-4/+4
| | | | llvm-svn: 219312
* [AVX512] Refactoring of avx512_binop_rm multiclass through AVX512_masking.Robert Khasanov2014-10-082-133/+60
| | | | | | | Added new argrument for AVX512_masking: InstrItinClass and bit isCommutable. No functional change. llvm-svn: 219310
* Emit unaligned access build attribute for ARMRenato Golin2014-10-081-0/+7
| | | | | | Patch by Charlie Turner. llvm-svn: 219301
* Refactor isThumb1Only() && isMClass() into a predicate called isV6M()Renato Golin2014-10-082-5/+8
| | | | | | | | | This must be enforced for all v6M cores, not just the cortex-m0, irregardless of the user-specified alignment. Patch by Charlie Turner. llvm-svn: 219300
* Simplify switch statement in ARM subtarget align accessRenato Golin2014-10-081-30/+24
| | | | | | | | This switch can be reduced to a simpler if/else statement. Patch by Charlie Turner. llvm-svn: 219299
* Use the TargetLowering information we already have on theEric Christopher2014-10-081-305/+256
| | | | | | | SelectionDAG in SelectionDAGBuilder rather than going through the TargetMachine for lookup. llvm-svn: 219292
* Grab the TargetRegisterInfo off of the subtarget from theEric Christopher2014-10-081-1/+1
| | | | | | | MachineFunction rather than a lookup on the TargetMachine to avoid unnecessary lookups. llvm-svn: 219291
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