[AVX512] Peel off an asm-only class from AVX512_masking_common.

No functional change.

This enables the generation of masking instructions that don't provide a
ISel pattern.

llvm-svn: 219358

1 files changed, 32 insertions, 10 deletions

diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td
index 40292f5dac1..c7126296c30 100644
--- a/llvm/lib/Target/X86/X86InstrAVX512.td
+++ b/llvm/lib/Target/X86/X86InstrAVX512.td
@@ -115,14 +115,18 @@ def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
                                              v2i64x_info>;
 
-
-// Common base class of AVX512_masking and AVX512_masking_3src.
-multiclass AVX512_masking_common<bits<8> O, Format F, X86VectorVTInfo _,
+// This multiclass generates the masking variants from the non-masking
+// variant.  It only provides the assembly pieces for the masking variants.
+// It assumes custom ISel patterns for masking which can be provided as
+// template arguments.
+multiclass AVX512_masking_custom<bits<8> O, Format F,
                                  dag Outs,
                                  dag Ins, dag MaskingIns, dag ZeroMaskingIns,
                                  string OpcodeStr,
                                  string AttSrcAsm, string IntelSrcAsm,
-                                 dag RHS, dag MaskingRHS,
+                                 list<dag> Pattern,
+                                 list<dag> MaskingPattern,
+                                 list<dag> ZeroMaskingPattern,
                                  string MaskingConstraint = "",
                                  InstrItinClass itin = NoItinerary,
                                  bit IsCommutable = 0> {
@@ -130,14 +134,14 @@ multiclass AVX512_masking_common<bits<8> O, Format F, X86VectorVTInfo _,
     def NAME: AVX512<O, F, Outs, Ins,
                        OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
                                      "$dst, "#IntelSrcAsm#"}",
-                       [(set _.RC:$dst, RHS)], itin>;
+                       Pattern, itin>;
 
   // Prefer over VMOV*rrk Pat<>
   let AddedComplexity = 20 in
     def NAME#k: AVX512<O, F, Outs, MaskingIns,
                        OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
                                      "$dst {${mask}}, "#IntelSrcAsm#"}",
-                       [(set _.RC:$dst, MaskingRHS)], itin>,
+                       MaskingPattern, itin>,
               EVEX_K {
       // In case of the 3src subclass this is overridden with a let.
       string Constraints = MaskingConstraint;
@@ -146,14 +150,32 @@ multiclass AVX512_masking_common<bits<8> O, Format F, X86VectorVTInfo _,
     def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
                        OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
                                      "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
-                       [(set _.RC:$dst,
-                             (vselect _.KRCWM:$mask, RHS,
-                                      (_.VT (bitconvert
-                                              (v16i32 immAllZerosV)))))],
+                       ZeroMaskingPattern,
                        itin>,
               EVEX_KZ;
 }
 
+
+// Common base class of AVX512_masking and AVX512_masking_3src.
+multiclass AVX512_masking_common<bits<8> O, Format F, X86VectorVTInfo _,
+                                 dag Outs,
+                                 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
+                                 string OpcodeStr,
+                                 string AttSrcAsm, string IntelSrcAsm,
+                                 dag RHS, dag MaskingRHS,
+                                 string MaskingConstraint = "",
+                                 InstrItinClass itin = NoItinerary,
+                                 bit IsCommutable = 0> :
+  AVX512_masking_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
+                        AttSrcAsm, IntelSrcAsm,
+                        [(set _.RC:$dst, RHS)],
+                        [(set _.RC:$dst, MaskingRHS)],
+                        [(set _.RC:$dst,
+                              (vselect _.KRCWM:$mask, RHS,
+                                       (_.VT (bitconvert
+                                               (v16i32 immAllZerosV)))))],
+                        MaskingConstraint, NoItinerary, IsCommutable>;
+
 // This multiclass generates the unconditional/non-masking, the masking and
 // the zero-masking variant of the instruction.  In the masking case, the
 // perserved vector elements come from a new dummy input operand tied to $dst.