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* [Allocator Cleanup] Move generic pointer alignment helper out of anChandler Carruth2014-03-281-15/+3
| | | | | | | out-of-line private static method and into the collection of inline alignment helpers in MathExtras.h. llvm-svn: 204995
* [Allocator Cleanup] Make the growth of the "slab" size of theChandler Carruth2014-03-281-17/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | BumpPtrAllocator significantly less strange by making it a simple function of the number of slabs allocated rather than by making it a recurrance. I *think* the previous behavior was essentially that the size of the slabs would be doubled after the first 128 were allocated, and then doubled again each time 64 more were allocated, but only if every allocation packed perfectly into the slab size. If not, the wasted space wouldn't be counted toward increasing the size, but allocations over the size threshold *would*. And since the allocations over the size threshold might be much larger than the slab size, this could have somewhat surprising consequences where we rapidly grow the slab size. This currently requires adding state to the allocator to track the number of slabs currently allocated, but that isn't too bad. I'm planning further changes to the allocator that will make this state fall out even more naturally. It still doesn't fully decouple the growth rate from the allocations which are over the size threshold. That fix is coming later. This specific fix will allow making the entire thing into a more stateless device and lifting the parameters into template parameters rather than runtime parameters. llvm-svn: 204993
* [cleanup] Hoist the initialization and constants for slab sizes to theChandler Carruth2014-03-281-20/+17
| | | | | | | | top of the default jit memory manager. This will allow them to be used as template parameters rather than runtime parameters in a subsequent commit. llvm-svn: 204992
* C++11: convert verbose loops to range-based loops.Adrian Prantl2014-03-271-7/+6
| | | | llvm-svn: 204981
* [PowerPC] Use a small cleanup pass to remove VSX self copiesHal Finkel2014-03-273-0/+78
| | | | | | | | | | | | As explained in r204976, because of how the allocation of VSX registers interacts with the call-lowering code, we sometimes end up generating self VSX copies. Specifically, things like this: %VSL2<def> = COPY %F2, %VSL2<imp-use,kill> (where %F2 is really a sub-register of %VSL2, and so this copy is a nop) This adds a small cleanup pass to remove these prior to post-RA scheduling. llvm-svn: 204980
* Provide a target override for the cost of using a callee-saved registerManman Ren2014-03-271-2/+6
| | | | | | | | | for the first time. Thanks Andy for the discussion. rdar://16162005 llvm-svn: 204979
* Canonicalise Windows target triple spellingsSaleem Abdulrasool2014-03-275-8/+35
| | | | | | | | | | | | | | | | | | | | | | | | | Construct a uniform Windows target triple nomenclature which is congruent to the Linux counterpart. The old triples are normalised to the new canonical form. This cleans up the long-standing issue of odd naming for various Windows environments. There are four different environments on Windows: MSVC: The MS ABI, MSVCRT environment as defined by Microsoft GNU: The MinGW32/MinGW32-W64 environment which uses MSVCRT and auxiliary libraries Itanium: The MSVCRT environment + libc++ built with Itanium ABI Cygnus: The Cygwin environment which uses custom libraries for everything The following spellings are now written as: i686-pc-win32 => i686-pc-windows-msvc i686-pc-mingw32 => i686-pc-windows-gnu i686-pc-cygwin => i686-pc-windows-cygnus This should be sufficiently flexible to allow us to target other windows environments in the future as necessary. llvm-svn: 204977
* [PowerPC] Don't remove self VSX copies in PPCInstrInfo::copyPhysRegHal Finkel2014-03-271-9/+13
| | | | | | | | | | | | | | | Because of how the allocation of VSX registers interacts with the call-lowering code, we sometimes end up generating self VSX copies. Specifically, things like this: %VSL2<def> = COPY %F2, %VSL2<imp-use,kill> (where %F2 is really a sub-register of %VSL2, and so this copy is a nop) The problem is that ExpandPostRAPseudos always assumes that *some* instruction has been inserted, and adds implicit defs to it. This is a problem if no copy was inserted because it can cause subtle problems during post-RA scheduling. These self copies will have to be removed some other way. llvm-svn: 204976
* [X86][Vector Cost Model] Add a comment to explain the workaroundQuentin Colombet2014-03-271-0/+5
| | | | | | | | in my previous commit (r204884). <rdar://problem/16381225> llvm-svn: 204972
* [PowerPC] Fix v2f64 vector extract and related patternsHal Finkel2014-03-272-4/+4
| | | | | | | | | First, v2f64 vector extract had not been declared legal (and so the existing patterns were not being used). Second, the patterns for that, and for scalar_to_vector, should really be a regclass copy, not a subregister operation, because the VSX registers directly hold both the vector and scalar data. llvm-svn: 204971
* [PowerPC] Expand v2i64 shiftsHal Finkel2014-03-271-0/+4
| | | | | | | | These operations need to be expanded during legalization so that isel does not crash. In theory, we might be able to custom lower some of these. That, however, would need to be follow-up work. llvm-svn: 204963
* Register Allocator: refactoring and add comments.Manman Ren2014-03-271-35/+58
| | | | | | | | No functionality change. Thanks Andy for reviewing. rdar://16162005 llvm-svn: 204962
* Remove another unused argument.Rafael Espindola2014-03-279-28/+20
| | | | llvm-svn: 204961
* DebugInfo: Support for compressed debug info sectionsDavid Blaikie2014-03-274-8/+67
| | | | | | | | | | | | | | | | | | | 1) When creating a .debug_* section and instead create a .zdebug_ section. 2) When creating a fragment in a .zdebug_* section, make it a compressed fragment. 3) When computing the size of a compressed section, compress the data and use the size of the compressed data. 4) Emit the compressed bytes. Also, check that only if a section has a compressed fragment, then that is the only fragment in the section. Assert-fail if the fragment's data is modified after it is compressed. Initial review on llvm-commits by Eric Christopher and Rafael Espindola. llvm-svn: 204958
* DebugInfo: TargetOptions/MCAsmInfo support for compressed debug info sectionsDavid Blaikie2014-03-271-0/+3
| | | | llvm-svn: 204957
* Remove unused argument.Rafael Espindola2014-03-279-41/+24
| | | | llvm-svn: 204956
* InstCombine: Don't combine constants on unsigned icmpsReid Kleckner2014-03-271-1/+2
| | | | | | | | | Fixes a miscompile introduced in r204912. It would miscompile code like (unsigned)(a + -49) <= 5U. The transform would turn this into (unsigned)a < 55U, which would return true for values in [0, 49], when it should not. llvm-svn: 204948
* R600: Implement isZExtFree.Matt Arsenault2014-03-272-0/+20
| | | | | | | This allows 64-bit operations that are truncated to be reduced to 32-bit ones. llvm-svn: 204946
* R600/SI: Fix unreachable with a sext_in_reg to an illegal type.Matt Arsenault2014-03-274-4/+28
| | | | llvm-svn: 204945
* [mips] Some uses of isMips64()/hasMips64() are really tests for 64-bit GPR'sDaniel Sanders2014-03-276-23/+23
| | | | | | | | | | | | Summary: No functional change since these predicates are (currently) synonymous. Extracted from a patch by David Chisnall His work was sponsored by: DARPA, AFRL Differential Revision: http://llvm-reviews.chandlerc.com/D3202 llvm-svn: 204943
* [AArch64] Lower SHL_PARTS, SRA_PARTS and SRL_PARTSLogan Chien2014-03-272-0/+91
| | | | | | | | Lower SHL_PARTS, SRA_PARTS and SRL_PARTS to perform 128-bit integer shift Patch by GuanHong Liu. llvm-svn: 204940
* Prevent alias from pointing to weak aliases.Rafael Espindola2014-03-2712-41/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds back r204781. Original message: Aliases are just another name for a position in a file. As such, the regular symbol resolutions are not applied. For example, given define void @my_func() { ret void } @my_alias = alias weak void ()* @my_func @my_alias2 = alias void ()* @my_alias We produce without this patch: .weak my_alias my_alias = my_func .globl my_alias2 my_alias2 = my_alias That is, in the resulting ELF file my_alias, my_func and my_alias are just 3 names pointing to offset 0 of .text. That is *not* the semantics of IR linking. For example, linking in a @my_alias = alias void ()* @other_func would require the strong my_alias to override the weak one and my_alias2 would end up pointing to other_func. There is no way to represent that with aliases being just another name, so the best solution seems to be to just disallow it, converting a miscompile into an error. llvm-svn: 204934
* [mips] Attempting to use register $32 should be an error instead of an ↵Daniel Sanders2014-03-271-1/+1
| | | | | | | | | | | | assertion. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3201 llvm-svn: 204932
* The forward declare should be a struct instead of a class (to be consistent ↵Aaron Ballman2014-03-271-1/+1
| | | | | | with the definition, as well as to silence an MSVC C4099 warning). llvm-svn: 204928
* [mips] Add support for .cpsetupDaniel Sanders2014-03-271-0/+133
| | | | | | | | | | | | | | Summary: Patch by Robert N. M. Watson His work was sponsored by: DARPA, AFRL Small corrections by myself. CC: theraven, matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3199 llvm-svn: 204924
* [mips] The decision between GOT_DISP and GOT16 for global addresses depends ↵Daniel Sanders2014-03-271-2/+2
| | | | | | | | | | | | | | on ABI rather than MIPS64 Summary: No functional change (for supported use cases) Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3191 llvm-svn: 204922
* Split the file MipsAsmBackend.cpp in Split the file MipsAsmBackend.cpp and ↵Zoran Jovanovic2014-03-272-195/+241
| | | | | | | | Split the file MipsAsmBackend.h. Differential Revision: http://llvm-reviews.chandlerc.com/D3134 llvm-svn: 204921
* All new elements except the last one initialized to NULL. Ideally, once ↵Karthik Bhat2014-03-271-7/+7
| | | | | | | | | parsing is complete, all elements should be non-NULL. To safe-guard BitcodeReader, this patch adds null check for all access to these list. Patch by Dinesh Dwivedi! llvm-svn: 204920
* [mips] Remove unused private field.Matheus Almeida2014-03-271-2/+1
| | | | llvm-svn: 204919
* [mips] NaCl should now use the custom MipsELFStreamer (recently added) in spiteMatheus Almeida2014-03-273-14/+18
| | | | | | | | | | | | | | of MCELFStreamer. This is so that changes to MipsELFStreamer will automatically propagate through its subclasses. No functional changes (MipsELFStreamer has the same functionality of MCELFStreamer at the moment). Differential Revision: http://llvm-reviews.chandlerc.com/D3130 llvm-svn: 204918
* [mips] Implement custom MCELFStreamer.Matheus Almeida2014-03-274-1/+66
| | | | | | | | | | | | | This allows us to insert some hooks before emitting data into an actual object file. For example, we can capture the register usage for a translation unit by overriding the EmitInstruction method. The register usage information is needed to generate .reginfo and .Mips.options ELF sections. No functional changes. Differential Revision: http://llvm-reviews.chandlerc.com/D3129 llvm-svn: 204917
* InstCombine: merge constants in both operands of icmp.Erik Verbruggen2014-03-272-12/+13
| | | | | | | | | | Transform: icmp X+Cst2, Cst into: icmp X, Cst-Cst2 when Cst-Cst2 does not overflow, and the add has nsw. llvm-svn: 204912
* [mips] Stop caching the result of hasMips64(), isABI_O32(), isABI_N32(), and ↵Daniel Sanders2014-03-273-55/+53
| | | | | | | | | | | | | | | | | | | isABI_N64() from MipsSubTarget in MipsTargetLowering Summary: The short name is quite convenient so provide an accessor for them instead. No functional change Depends on D3177 Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3178 llvm-svn: 204911
* AVX-512: Implemented masking for integer arithmetic & logic instructions.Elena Demikhovsky2014-03-272-94/+276
| | | | | | By Robert Khasanov rob.khasanov@gmail.com llvm-svn: 204906
* Rejected r204899 and r204900 due to remaining test failures on ↵Stepan Dyatkovskiy2014-03-271-17/+1
| | | | | | cmake-llvm-x86_64-linux buildbot. llvm-svn: 204901
* Fix for pr18931: Crash using integrated assembler with immediate arithmeticStepan Dyatkovskiy2014-03-271-1/+17
| | | | | | | | | | | Fix description: Expressions like 'cmp r0, #(l1 - l2) >> 3' could not be evaluated on asm parsing stage, since it is impossible to resolve labels on this stage. In the end of stage we still have expression (MCExpr). Then, when we want to encode it, we expect it to be an immediate, but it still an expression. Patch introduces a Fixup (MCFixup instance), that is processed after main encoding stage. llvm-svn: 204899
* ARM: raise error message when complex SO expressions can't really beJiangning Liu2014-03-271-1/+1
| | | | | | solved as a constant at compilation time. llvm-svn: 204898
* Move MCSymbolizer's constructor into header. It's trivial - there's no need forLang Hames2014-03-271-5/+0
| | | | | | it to be out-of-line. llvm-svn: 204892
* Update MCSymbolizer and its subclasses' constructors to reflect the fact thatLang Hames2014-03-274-17/+19
| | | | | | they take ownership of the RelocationInfo they're constructed with. llvm-svn: 204891
* Remove forward declaration for Target class - Target is already defined here.Lang Hames2014-03-271-3/+0
| | | | | | No functional change. llvm-svn: 204885
* [X86][Vectorizer Cost Model] Correct vectorization cost model for v2i64->v2f64Quentin Colombet2014-03-271-0/+2
| | | | | | | | | | and v4i64->v4f64. The new costs match what we did for SSE2 and reflect the reality of our codegen. <rdar://problem/16381225> llvm-svn: 204884
* Correctly propagates st_size.Rafael Espindola2014-03-271-7/+6
| | | | | | This also finally removes a bogus call to AliasedSymbol. llvm-svn: 204883
* X86: Correct vectorization cost model for v8f32->v8i8.Jim Grosbach2014-03-271-1/+1
| | | | | | | | Fix the cost model to reflect the reality of our codegen. rdar://16370633 llvm-svn: 204880
* Treat lifetime.start'd memory like we treat freshly alloca'd memory. Patch ↵Nick Lewycky2014-03-261-4/+16
| | | | | | by Björn Steinbrink! llvm-svn: 204876
* [PowerPC] Generate VSX permutations for v2[fi]64 vectorsHal Finkel2014-03-263-5/+45
| | | | llvm-svn: 204873
* CloneFunction: Clone all attributes, including the CCReid Kleckner2014-03-261-14/+16
| | | | | | | | | | | | | | | | Summary: Tested with a unit test because we don't appear to have any transforms that use this other than ASan, I think. Fixes PR17935. Reviewers: nicholas CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D3194 llvm-svn: 204866
* This is a fix for PR# 19051. I noticed code gen differences due to code ↵Ekaterina Romanova2014-03-261-1/+1
| | | | | | motion when running tests with and without the debug info at O2. The problem is in branch folding. A loop wanted to skip the debug info, but actually it didn't do so. llvm-svn: 204865
* Add comments. Addressing review comments from Evan on r204690.Manman Ren2014-03-261-0/+5
| | | | llvm-svn: 204864
* llvm-cov: Handle functions with no line numberJustin Bogner2014-03-261-0/+5
| | | | | | | | | Functions may in an instrumented binary but not in the original source when they're inserted by the compiler or the runtime. These functions aren't meaningful to the user, so teach llvm-cov to skip over them instead of crashing. llvm-svn: 204863
* Fix a problem with the ARM assembler incorrectly matching aKevin Enderby2014-03-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | vector list parameter that is using all lanes "{d0[], d2[]}" but can match and instruction with a ”{d0, d2}" parameter. I’m finishing up a fix for proper checking of the unsupported alignments on vld/vst instructions and ran into this. Thus I don’t have a test case at this time. And adding all code that will demonstrate the bug would obscure the very simple one line fix. So if you would indulge me on not having a test case at this time I’ll instead offer up a detailed explanation of what is going on in this commit message. This instruction: vld2.8 {d0[], d2[]}, [r4:64] is not legal as the alignment can only be 16 when the size is 8. Per this documentation: A8.8.325 VLD2 (single 2-element structure to all lanes) <align> The alignment. It can be one of: 16 2-byte alignment, available only if <size> is 8, encoded as a = 1. 32 4-byte alignment, available only if <size> is 16, encoded as a = 1. 64 8-byte alignment, available only if <size> is 32, encoded as a = 1. omitted Standard alignment, see Unaligned data access on page A3-108. So when code is added to the llvm integrated assembler to not match that instruction because of the alignment it then goes on to try to match other instructions and comes across this: vld2.8 {d0, d2}, [r4:64] and and matches it. This is because of the method ARMOperand::isVecListDPairSpaced() is missing the check of the Kind. In this case the Kind is k_VectorListAllLanes . While the name of the method may suggest that this is OK it really should check that the Kind is k_VectorList. As the method ARMOperand::isDoubleSpacedVectorAllLanes() is what was used to match {d0[], d2[]} and correctly checks the Kind: bool isDoubleSpacedVectorAllLanes() const { return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced; } where the original ARMOperand::isVecListDPairSpaced() does not check the Kind: bool isVecListDPairSpaced() const { if (isSingleSpacedVectorList()) return false; return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID] .contains(VectorList.RegNum)); } Jim Grosbach has reviewed the change and said: Yep, that sounds right. … And by "right" I mean, "wow, that's a nasty latent bug I'm really, really glad to see fixed." :) rdar://16436683 llvm-svn: 204861
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