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* [LV] Ignore the cost of values that will not appear in the vectorized loopDorit Nuzman2017-12-121-1/+2
| | | | | | | | | VecValuesToIgnore holds values that will not appear in the vectorized loop. We should therefore ignore their cost when VF > 1. Differential Revision: https://reviews.llvm.org/D40883 llvm-svn: 320463
* [X86] Use regular expressions more aggressively to reduce the number of ↵Craig Topper2017-12-124-1032/+48
| | | | | | | | | | scheduler entries needed for FMA3 instructions. When the scheduler tables are generated by tablegen, the instructions are divided up into groups based on their default scheduling information and how they are referenced by groups for each processor. For any set of instructions that are matched by a specific InstRW line, that group of instructions is guaranteed to not be in a group with any other instructions. So in general, the more InstRW class definitions are created, the more groups we end up with in the generated files. Particularly if a lot of the InstRW lines only match to single instructions, which is true of a large number of the Intel scheduler models. This change alone reduces the number of instructions groups from ~6000 to ~5500. And there's lots more we could do. llvm-svn: 320461
* [CallSiteSplitting] Don't let debug intrinsics affect optimizationsMikael Holmen2017-12-121-4/+5
| | | | | | | | | | | | | | | | | Summary: This solves PR35616. We don't want the compiler to generate different code when we compile with/without -g, so we now ignore debug intrinsics when determining if the optimization can trigger or not. Reviewers: junbuml Subscribers: davide, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D41068 llvm-svn: 320460
* [X86] Use Ld scheduler classes for instructions with folded loads.Craig Topper2017-12-123-41/+41
| | | | llvm-svn: 320459
* [X86] Correct the FMA3 regular expressions in the znver1 scheduler model.Craig Topper2017-12-121-4/+4
| | | | llvm-svn: 320458
* Reland "[WebAssembly] Import the linear memory and function table."Sam Clegg2017-12-111-40/+42
| | | | | | Original change: https://reviews.llvm.org/D40875 llvm-svn: 320432
* Revert r318704 - [Sparc] efficient pattern for UINT_TO_FP conversionRichard Trieu2017-12-113-92/+29
| | | | | | | | See bug https://bugs.llvm.org/show_bug.cgi?id=35631 r318704 is giving a fatal error on some code with unsigned to floating point conversions. llvm-svn: 320429
* LSR: Check more intrinsic pointer operandsMatt Arsenault2017-12-113-22/+73
| | | | llvm-svn: 320424
* Revert r320407 "[InstCombine] Fix PR35618: Instcombine hangs on single ↵Hans Wennborg2017-12-111-17/+2
| | | | | | | | | | | | | | | | | | | | | minmax load bitcast." The tests fail (opt asserts) on Windows. > Summary: > If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1, > &V2)))), bitcast)`, but the load is used in other instructions, it leads > to looping in InstCombiner. Patch adds additional check that all users > of the load instructions are stores and then replaces all uses of load > instruction by the new one with new type. > > Reviewers: RKSimon, spatel, majnemer > > Subscribers: llvm-commits > > Differential Revision: https://reviews.llvm.org/D41072 llvm-svn: 320421
* [CodeGen] Improve the consistency of instruction fusion*Evandro Menezes2017-12-111-24/+55
| | | | | | | | | | | When either instruction in a fused pair has no other dependency, besides on the other instruction, make sure that other instructions do not get scheduled between them. Additionally, avoid fusing an instruction more than once along the same dependency chain. Differential revision: https://reviews.llvm.org/D36704 llvm-svn: 320420
* ASAN: Provide reliable debug info for local variables at -O0.Adrian Prantl2017-12-111-2/+12
| | | | | | | | | | | | | | | | | | | | | | The function stack poisioner conditionally stores local variables either in an alloca or in malloc'ated memory, which has the unfortunate side-effect, that the actual address of the variable is only materialized when the variable is accessed, which means that those variables are mostly invisible to the debugger even when compiling without optimizations. This patch stores the address of the local stack base into an alloca, which can be referred to by the debug info and is available throughout the function. This adds one extra pointer-sized alloca to each stack frame (but mem2reg can optimize it away again when optimizations are enabled, yielding roughly the same debug info quality as before in optimized code). rdar://problem/30433661 Differential Revision: https://reviews.llvm.org/D41034 llvm-svn: 320415
* [PowerPC] Partially enable the ISEL expansion pass.Tony Jiang2017-12-111-21/+64
| | | | | | | | | | | The pass to expand ISEL instructions into if-then-else sequences in patch D23630 is currently disabled. This patch partially enable it by always removing the unnecessary ISELs (all registers used by the ISELs are the same one) and folding the ISELs which have the same input registers into unconditional copies. Differential Revision: https://reviews.llvm.org/D40497 llvm-svn: 320414
* [InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.Alexey Bataev2017-12-111-2/+17
| | | | | | | | | | | | | | | | | Summary: If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1, &V2)))), bitcast)`, but the load is used in other instructions, it leads to looping in InstCombiner. Patch adds additional check that all users of the load instructions are stores and then replaces all uses of load instruction by the new one with new type. Reviewers: RKSimon, spatel, majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41072 llvm-svn: 320407
* [Hexagon] Add support for Hexagon V65Krzysztof Parzyszek2017-12-1152-5590/+11596
| | | | llvm-svn: 320404
* [dwarfdump] Fix off-by-one bug in accelerator table extractor.Jonas Devlieghere2017-12-113-8/+14
| | | | | | | | | | | | | | | This fixes a bug where the verifier was complaining about empty accelerator tables. When the table is empty, its size is not a valid offset as it points after the end of the section. This patch also makes the extractor return llvm:Error instead of bool for better error reporting in the verifier. Differential revision: https://reviews.llvm.org/D41063 rdar://35932007 llvm-svn: 320399
* Normalize line endings. NFCI.Simon Pilgrim2017-12-111-30/+30
| | | | llvm-svn: 320389
* [GlobalISel] Disable GISel for big endian.Amara Emerson2017-12-111-0/+9
| | | | | | | | | | | | | This is due to PR26161 needing to be resolved before we can fix big endian bugs like PR35359. The work to split aggregates into smaller LLTs instead of using one large scalar will take some time, so in the mean time we'll fall back to SDAG. Some ARM BE tests xfailed for now as a result. Differential Revision: https://reviews.llvm.org/D40789 llvm-svn: 320388
* [X86] Add LWP schedule testsSimon Pilgrim2017-12-111-2/+2
| | | | | | Tag LWP instructions as WriteSystem llvm-svn: 320387
* [MSan] Hotfix compilationAlexander Potapenko2017-12-111-2/+2
| | | | | | | For some reason the override directives got removed in r320373. I suspect this to be an unwanted effect of clang-format. llvm-svn: 320381
* [AMDGPU][MC][GFX9] Corrected encoding of ttmp registers, disabled tba/tmaDmitry Preobrazhensky2017-12-118-69/+164
| | | | | | | | | | | | See bugs 35494 and 35559: https://bugs.llvm.org/show_bug.cgi?id=35494 https://bugs.llvm.org/show_bug.cgi?id=35559 Reviewers: vpykhtin, artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D41007 llvm-svn: 320375
* [DAGCombiner] protect against an infinite loop between shl <--> mul (PR35579)Sanjay Patel2017-12-111-1/+2
| | | | | | | | | | | | | | | | | | | | | | | At first, I tried to thread the x86 needle and use a target hook (isVectorShiftByScalarCheap()) to disable the transform only for non-splat pow-of-2 constants, but not AVX2, but only some element types, but...it's difficult. Here we just avoid the loop with the x86 vector transform that conflicts with the general DAG combine and preserve all of the existing behavior AFAICT otherwise. Some tests that will probably fail if someone does try to restrict this in a more targeted way for x86-only may be found in: test/CodeGen/X86/combine-mul.ll test/CodeGen/X86/vector-mul.ll test/CodeGen/X86/widen_arith-5.ll This should prevent the infinite looping seen with: https://bugs.llvm.org/show_bug.cgi?id=35579 Differential Revision: https://reviews.llvm.org/D41040 llvm-svn: 320374
* [MSan] introduce getShadowOriginPtr(). NFC.Alexander Potapenko2017-12-111-129/+191
| | | | | | | | | | | | | | This patch introduces getShadowOriginPtr(), a method that obtains both the shadow and origin pointers for an address as a Value pair. The existing callers of getShadowPtr() and getOriginPtr() are updated to use getShadowOriginPtr(). The rationale for this change is to simplify KMSAN instrumentation implementation. In KMSAN origins tracking is always enabled, and there's no direct mapping between the app memory and the shadow/origin pages. Both the shadow and the origin pointer for a given address are obtained by calling a single runtime hook from the instrumentation, therefore it's easier to work with those pointers together. Reviewed at https://reviews.llvm.org/D40835. llvm-svn: 320373
* [Hexagon] Crash in instruction selection for insert_vector_elt for HVXKrzysztof Parzyszek2017-12-111-1/+1
| | | | | | | | A wrong type was passed to insertVector, causing an out-of-bounds value to be added an an operand to HexagonISD::INSERT. This later failed in instruction selection. llvm-svn: 320369
* [PowerPC] Sign-extend negative constant storesNemanja Ivanovic2017-12-111-2/+6
| | | | | | | | | | | | | Second part of https://reviews.llvm.org/D40348. Revision r318436 has extended all constants feeding a store to 64 bits to allow for CSE on the SDAG. However, negative constants were zero extended which made the constant being loaded appear to be a positive value larger than 16 bits. This resulted in long sequences to materialize such constants rather than simply a "load immediate". This patch just sign-extends those updated constants so that they remain 16-bit signed immediates if they started out that way. llvm-svn: 320368
* [DAGCombiner] Add combined indexed load to the work listNemanja Ivanovic2017-12-111-0/+1
| | | | | | | | | | This commit is the first part of https://reviews.llvm.org/D40348. In order to allow target combines to be performed on newly combined indexed loads, add them back to the worklist. The remainder of the above patch will be committed in subsequent revisions and will use this. Test cases will be included with those follow-up commits. llvm-svn: 320365
* [RISCV] Add custom CC_RISCV calling convention and improved call supportAlex Bradbury2017-12-114-48/+373
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The TableGen-based calling convention definitions are inflexible, while writing a function to implement the calling convention is very straight-forward, and allows difficult cases to be handled more easily. With this patch adds support for: * Passing large scalars according to the RV32I calling convention * Byval arguments * Passing values on the stack when the argument registers are exhausted The custom CC_RISCV calling convention is also used for returns. This patch also documents the ABI lowering that a language frontend is expected to perform. I would like to work to simplify these requirements over time, but this will require further discussion within the LLVM community. We add PendingArgFlags CCState, as a companion to PendingLocs. The PendingLocs vector is used by a number of backends to handle arguments that are split during legalisation. However CCValAssign doesn't keep track of the original argument alignment. Therefore, add a PendingArgFlags vector which can be used to keep track of the ISD::ArgFlagsTy for every value added to PendingLocs. Differential Revision: https://reviews.llvm.org/D39898 llvm-svn: 320359
* [RISCV] Allow lowering of dynamic_stackalloc, stacksave, stackrestoreAlex Bradbury2017-12-111-0/+5
| | | | llvm-svn: 320358
* [RISCV] Implement prolog and epilog insertionAlex Bradbury2017-12-112-3/+159
| | | | | | | | | | As frame pointer elimination isn't implemented until a later patch and we make extensive use of update_llc_test_checks.py, this changes touches a lot of the RISC-V tests. Differential Revision: https://reviews.llvm.org/D39849 llvm-svn: 320357
* [ARM] Use ADDCARRY / SUBCARRYRoger Ferrer Ibanez2017-12-113-21/+171
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a preparatory step for D34515. This change: - makes nodes ISD::ADDCARRY and ISD::SUBCARRY legal for i32 - lowering is done by first converting the boolean value into the carry flag using (_, C) ← (ARMISD::ADDC R, -1) and converted back to an integer value using (R, _) ← (ARMISD::ADDE 0, 0, C). An ARMISD::ADDE between the two operations does the actual addition. - for subtraction, given that ISD::SUBCARRY second result is actually a borrow, we need to invert the value of the second operand and result before and after using ARMISD::SUBE. We need to invert the carry result of ARMISD::SUBE to preserve the semantics. - given that the generic combiner may lower ISD::ADDCARRY and ISD::SUBCARRYinto ISD::UADDO and ISD::USUBO we need to update their lowering as well otherwise i64 operations now would require branches. This implies updating the corresponding test for unsigned. - add new combiner to remove the redundant conversions from/to carry flags to/from boolean values (ARMISD::ADDC (ARMISD::ADDE 0, 0, C), -1) → C - fixes PR34045 - fixes PR34564 - fixes PR35103 Differential Revision: https://reviews.llvm.org/D35192 llvm-svn: 320355
* [RISCV] Support lowering FrameIndexAlex Bradbury2017-12-118-29/+104
| | | | | | | | | | | | | | | | Introduces the AddrFI "addressing mode", which is necessary simply because it's not possible to write a pattern that directly matches a frameindex. Ensure callee-saved registers are accessed relative to the stackpointer. This is necessary as callee-saved register spills are performed before the frame pointer is set. Move HexagonDAGToDAGISel::isOrEquivalentToAdd to SelectionDAGISel, so we can make use of it in the RISC-V backend. Differential Revision: https://reviews.llvm.org/D39848 llvm-svn: 320353
* [mips] Removal of microMIPS64R6Aleksandar Beserminji2017-12-1120-1072/+113
| | | | | | | | | | | All files and parts of files related to microMIPS4R6 are removed. When target is microMIPS4R6, errors are printed. This is LLVM part of patch. Differential Revision: https://reviews.llvm.org/D35625 llvm-svn: 320350
* [AVR] Implement some missing code pathsDylan McKay2017-12-112-4/+19
| | | | | | This has been broken since r320009. llvm-svn: 320348
* [AVR] Fix incorrectly-calculated AVRMCExpr evaluationsDylan McKay2017-12-111-12/+9
| | | | | | This has been broken since r320009. llvm-svn: 320347
* [DAGCombiner] Support folding (mulhs/u X, 0)->0 for vectors.Craig Topper2017-12-111-0/+16
| | | | | | We should probably also fold (mulhs/u X, 1) for vectors, but that's harder. llvm-svn: 320344
* [DAGCombiner] Reuse existing SDLoc variable instead of creating a new one. NFCCraig Topper2017-12-111-4/+3
| | | | llvm-svn: 320343
* [X86] Add VCOMISDZrr, VCOMISSZrr, VUCOMISDZrr, and VUCOMISSZrr to the ↵Craig Topper2017-12-101-4/+4
| | | | | | skylake server sheduler model llvm-svn: 320326
* [X86] Rename some instructions that start with Int_ to have the _Int at the end.Craig Topper2017-12-109-199/+199
| | | | | | | | This matches AVX512 version and is more consistent overall. And improves our scheduler models. In some cases this adds _Int to instructions that didn't have any Int_ before. It's a side effect of the adjustments made to some of the multiclasses. llvm-svn: 320325
* [X86][X87] Fix typo in znver1 FIST/FISTT schedule patternsSimon Pilgrim2017-12-101-1/+1
| | | | llvm-svn: 320322
* [X86] Rename some instructions from 'rb' to 'rrb' to make 'b' a proper ↵Craig Topper2017-12-102-17/+17
| | | | | | | | suffix. Fix the scheduling information for some of them. Some of the scheduling information was only present for the 'rb' version' and not the 'rr' version. Now we match 'rr(b?)' llvm-svn: 320320
* [X86] Add VCVTQQ2PS to the skylake server scheduler models.Craig Topper2017-12-101-0/+6
| | | | llvm-svn: 320319
* [X86] Add VPMULLWZ256 to the skylake server scheduler modelCraig Topper2017-12-101-0/+2
| | | | llvm-svn: 320318
* [X86] Add 256/512-bit EVEX VPSADBW instructions to skylake server scheduler ↵Craig Topper2017-12-101-2/+4
| | | | | | model. llvm-svn: 320317
* [X86] Fix a few instructions that were named Z512 instead of just Z.Craig Topper2017-12-104-15/+15
| | | | | | This makes things consistent with our normal instruction naming. llvm-svn: 320316
* [X86] Add VPSRLWZrr to skylake server scheduler model.Craig Topper2017-12-101-0/+1
| | | | llvm-svn: 320315
* [X86] Add VPUNPCKLWDZrr to skylake server scheduler model.Craig Topper2017-12-101-0/+1
| | | | llvm-svn: 320314
* [X86] Adjust tablegen includes so we can use Instructions in scheduler ↵Craig Topper2017-12-102-26/+25
| | | | | | | | models instead of just instregexs. This separates the CPU specific scheduler model includes to occur after the instructions. Moves the instruction includes between the basic scheduler information and the CPU specific scheduler models. llvm-svn: 320313
* [SimplifyLibCalls] propagate FMF when folding pow(x, -1.0) callSanjay Patel2017-12-101-14/+11
| | | | | | | Follow-up for a bug that's similar to: https://bugs.llvm.org/show_bug.cgi?id=35601 llvm-svn: 320312
* [SimplifyLibCalls] propagate FMF when folding pow(x, 2.0) call (PR35601)Sanjay Patel2017-12-101-1/+6
| | | | | | | This should fix the larger problem with sqrt shown in: https://bugs.llvm.org/show_bug.cgi?id=35601 llvm-svn: 320310
* [X86] Flag BroadWell scheduler model as completeSimon Pilgrim2017-12-101-4/+3
| | | | | | Locally tag COPY as WriteMove, which has caused some reg-reg + reg-mem instruction tests to reorder. llvm-svn: 320308
* Strip trailing whitespace. NFCI.Simon Pilgrim2017-12-101-3/+3
| | | | llvm-svn: 320306
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