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authorSimon Pilgrim <llvm-dev@redking.me.uk>2017-12-11 16:47:21 +0000
committerSimon Pilgrim <llvm-dev@redking.me.uk>2017-12-11 16:47:21 +0000
commitfabe354b42f90289dea877eb2dd85fa75d492817 (patch)
tree1ed8ada935db41c914153e72dfcd7fd4c1d8ff39 /llvm/lib
parent67644be6924c9a710260ec493366c13b95262c8e (diff)
downloadbcm5719-llvm-fabe354b42f90289dea877eb2dd85fa75d492817.tar.gz
bcm5719-llvm-fabe354b42f90289dea877eb2dd85fa75d492817.zip
[X86] Add LWP schedule tests
Tag LWP instructions as WriteSystem llvm-svn: 320387
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/X86/X86InstrInfo.td4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td
index 806a2e0380f..54231662808 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.td
+++ b/llvm/lib/Target/X86/X86InstrInfo.td
@@ -2567,7 +2567,7 @@ let Predicates = [HasTBM] in {
//===----------------------------------------------------------------------===//
// Lightweight Profiling Instructions
-let Predicates = [HasLWP] in {
+let Predicates = [HasLWP], SchedRW = [WriteSystem] in {
def LLWPCB : I<0x12, MRM0r, (outs), (ins GR32:$src), "llwpcb\t$src",
[(int_x86_llwpcb GR32:$src)], IIC_LWP>,
@@ -2615,7 +2615,7 @@ multiclass lwpval_intr<RegisterClass RC, Intrinsic Int> {
defm LWPVAL32 : lwpval_intr<GR32, int_x86_lwpval32>;
defm LWPVAL64 : lwpval_intr<GR64, int_x86_lwpval64>, VEX_W;
-} // HasLWP
+} // HasLWP, SchedRW
//===----------------------------------------------------------------------===//
// MONITORX/MWAITX Instructions
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