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* [WebAssembly] Tidy up `let` statements in .td files (NFC)Heejin Ahn2019-02-065-71/+59
| | | | | | | | | | | | | | | | | Summary: - Delete {} for one-line `let` statements - Don't indent within `let` blocks - Add comments after `let` block's closing braces Reviewers: tlively Subscribers: dschuff, sbc100, jgravelle-google, sunfish, jfb, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57730 llvm-svn: 353248
* [BasicAA] Cache nonEscapingLocalObjects for alias() calls.Alina Sbirlea2019-02-051-7/+27
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: Use a small cache for Values tested by nonEscapingLocalObject(). Since the calls to PointerMayBeCaptured are fairly expensive, this saves a good amount of compile time for anything relying heavily on BasicAA.alias() calls. This uses the same approach as the AliasCache, i.e. the cache is reset after each alias() call. The cache is not used or updated by modRefInfo calls since it's harder to know when to reset the cache. Testcases that show improvements with this patch are too large to include. Example compile time improvement: 7s to 6s. Reviewers: chandlerc, sunfish Subscribers: sanjoy, jlebar, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57627 llvm-svn: 353245
* [HotColdSplit] Do not split out `resume` instructionsVedant Kumar2019-02-051-2/+6
| | | | | | | | | Resumes that are not reachable from a cleanup landing pad are considered to be unreachable. It’s not safe to split them out. rdar://47808235 llvm-svn: 353242
* [ADT] Add a fallible_iterator wrapper.Lang Hames2019-02-051-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A fallible iterator is one whose increment or decrement operations may fail. This would usually be supported by replacing the ++ and -- operators with methods that return error: class MyFallibleIterator { public: // ... Error inc(); Errro dec(); // ... }; The downside of this style is that it no longer conforms to the C++ iterator concept, and can not make use of standard algorithms and features such as range-based for loops. The fallible_iterator wrapper takes an iterator written in the style above and adapts it to (mostly) conform with the C++ iterator concept. It does this by providing standard ++ and -- operator implementations, returning any errors generated via a side channel (an Error reference passed into the wrapper at construction time), and immediately jumping the iterator to a known 'end' value upon error. It also marks the Error as checked any time an iterator is compared with a known end value and found to be inequal, allowing early exit from loops without redundant error checking*. Usage looks like: MyFallibleIterator I = ..., E = ...; Error Err = Error::success(); for (auto &Elem : make_fallible_range(I, E, Err)) { // Loop body is only entered when safe. // Early exits from loop body permitted without checking Err. if (SomeCondition) return; } if (Err) // Handle error. * Since failure causes a fallible iterator to jump to end, testing that a fallible iterator is not an end value implicitly verifies that the error is a success value, and so is equivalent to an error check. Reviewers: dblaikie, rupprecht Subscribers: mgorny, dexonsmith, kristina, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57618 llvm-svn: 353237
* [InstCombine] limit extracting shuffle transform based on usesSanjay Patel2019-02-051-0/+5
| | | | | | | | | | As discussed in D53037, this can lead to worse codegen, and we don't generally expect the backend to be able to optimize arbitrary shuffles. If there's only one use of the 1st shuffle, that means it's getting removed, so that should always be safe. llvm-svn: 353235
* [PGO] Use a function for creating variable for profile file name. NFC.Rong Xu2019-02-052-16/+19
| | | | | | | Factored out the code for creating variable for profile file name to a function. llvm-svn: 353230
* [NFC][GlobalISel]: Add a convenience method to MachineInstrBuilder to ↵Aditya Nandakumar2019-02-052-2/+2
| | | | | | | | | | | | simplify getOperand(i).getReg() https://reviews.llvm.org/D57608 It's a common pattern in GISel to have a MachineInstrBuilder from which we get various regs (commonly MIB->getOperand(0).getReg()). This adds a helper method and the above can be replaced with MIB.getReg(0). llvm-svn: 353223
* [MC] Don't error on numberless .file directives on MachOReid Kleckner2019-02-051-4/+5
| | | | | | | | | | | | | | | | | | | | | | Summary: Before r349976, MC ignored such directives when producing an object file and asserted when re-producing textual assembly output. I turned this assertion into a hard error in both cases in r349976, but this makes it unnecessarily difficult to write a single assembly file that supports both MachO and other object formats that support .file. A user reported this as PR40578, and we decided to go back to ignoring the directive. Fixes PR40578 Reviewers: mstorsjo Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57772 llvm-svn: 353218
* [WebAssembly] Lower memmove to memory.copyThomas Lively2019-02-053-1/+17
| | | | | | | | | | | | | | Summary: The lowering is identical to the memcpy lowering. Reviewers: aheejin Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57727 llvm-svn: 353216
* [TargetLibraryInfo] Regroup run time functions for Windows (NFC)Evandro Menezes2019-02-051-38/+37
| | | | | | Regroup supported and unsupported functions by precision and C standard. llvm-svn: 353213
* GlobalISel: Verify G_GEPMatt Arsenault2019-02-051-0/+16
| | | | llvm-svn: 353209
* [AMDGPU] Consider XOR in waterfall loop as a terminatorScott Linder2019-02-051-1/+1
| | | | | | | | Ensure the XOR in the waterfall loop for indirect addressing is considered a terminator. Differential Revision: https://reviews.llvm.org/D57703 llvm-svn: 353207
* [DEBUG_INFO][NVPTX] Generate DW_AT_address_class to get the values in debugger.Alexey Bataev2019-02-052-2/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: According to https://docs.nvidia.com/cuda/archive/10.0/ptx-writers-guide-to-interoperability/index.html#cuda-specific-dwarf, the compiler should emit the DW_AT_address_class attribute for all variable and parameter. It means, that DW_AT_address_class attribute should be used in the non-standard way to support compatibility with the cuda-gdb debugger. Clang is able to generate the information about the variable address class. This information is emitted as the expression sequence `DW_OP_constu <DWARF Address Space> DW_OP_swap DW_OP_xderef`. The patch tries to find all such expressions and transform them into `DW_AT_address_class <DWARF Address Space>` if target is NVPTX and the debugger is gdb. If the expression is not found, then default values are used. For the local variables <DWARF Address Space> is set to ADDR_local_space(6), for the globals <DWARF Address Space> is set to ADDR_global_space(5). The values are taken from the table in the same section 5.2. CUDA-Specific DWARF Definitions. Reviewers: echristo, probinson Subscribers: jholewinski, aprantl, llvm-commits Differential Revision: https://reviews.llvm.org/D57157 llvm-svn: 353203
* AMDGPU: Fix assert on trunc from bitcast of build_vectorMatt Arsenault2019-02-051-1/+1
| | | | | | | | | The v2i64 argument is lowered to a bitcast of v4i32 build_vector. This would then attempt to use the i32-element as the source of the vector truncate. This really would need to collect 2 elements from the build_vector to produce the intended truncate. llvm-svn: 353202
* [X86][SSE] Disable ZERO_EXTEND shuffle combiningSimon Pilgrim2019-02-051-2/+2
| | | | | | rL352997 enabled ZERO_EXTEND from non-shuffle-able value types. I've disabled it for now to fix a regression identified by @asbirlea until I can fix this properly. llvm-svn: 353198
* [LLVM-C] Add Bindings to GlobalIFuncRobert Widmann2019-02-051-0/+65
| | | | | | | | | | | | | | | | | Summary: Adds the standard gauntlet of accessors for global indirect functions and updates the echo test. Now it would be nice to have a target abstraction so one could know if they have access to a suitable ELF linker and runtime. Reviewers: whitequark, deadalnix Reviewed By: whitequark Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D56177 llvm-svn: 353193
* Enable integrated assembler on MSP430 by default.Anton Korobeynikov2019-02-051-0/+1
| | | | | | | | Patch by Kristina Bessonova! Differential Revision: https://reviews.llvm.org/D56787 llvm-svn: 353192
* [AArch64][Outliner] Don't outline BTI instructionsOliver Stannard2019-02-051-0/+8
| | | | | | | | | | | We can't outline BTI instructions, because they need to be the very first instruction executed after an indirect call or branch. If we outline them, then an indirect call might go to the branch to the outlined function, which will fault. Differential revision: https://reviews.llvm.org/D57753 llvm-svn: 353190
* [X86][AVX] Attempt to combine shuffles to subvector broadcast loadSimon Pilgrim2019-02-051-0/+18
| | | | llvm-svn: 353189
* AArch64/GlobalISel: Don't clamp from 2 to 2Matt Arsenault2019-02-051-2/+2
| | | | | | This is equivalent to clampMaxNumElements, but saves a check. llvm-svn: 353188
* [WebAssembly] Object: Remove redundant method. NFC.Sam Clegg2019-02-051-5/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D57719 llvm-svn: 353183
* Recommit: Add support for prefix-only CLI optionsThomas Preud'homme2019-02-051-5/+14
| | | | | | | | | | | | | | | | | | | | | | Summary: Add support for options that always prefix their value, giving an error if the value is in the next argument or if the option is given a value assignment (ie. opt=val). This is the desired behavior for the -D option of FileCheck for instance. Copyright: - Linaro (changes in version 2 of revision D55940) - GraphCore (changes in later versions and introduced when creating D56549) Reviewers: jdenny Subscribers: llvm-commits, probinson, kristina, hiraditya, JonChesterfield Differential Revision: https://reviews.llvm.org/D56549 llvm-svn: 353172
* [MCA] Moved the logic that updates register dependencies from DispatchStage ↵Andrea Di Biagio2019-02-053-26/+20
| | | | | | | | | | | to RegisterFile. NFC DispatchStage should always delegate to an object of class RegisterFile the task of updating data dependencies. ReadState and WriteState objects should not be modified directly by DispatchStage. This patch also renames stage IS_AVAILABLE to IS_DISPATCHED. llvm-svn: 353170
* [X86][SSE] Add SimplifyDemandedVectorElts support for X86ISD::BLENDVSimon Pilgrim2019-02-051-0/+21
| | | | llvm-svn: 353165
* [MCA] Simplify the logic in method WriteState::addUser. NFCIAndrea Di Biagio2019-02-051-5/+1
| | | | | | | | In some cases, it is faster to just grow the set of 'Users' rather than performing a llvm::find_if every time a new user is added to the set. No functional change intended. llvm-svn: 353162
* [DebugInfo][NFCI] Split salvageDebugInfo into helper functionsJeremy Morse2019-02-051-82/+82
| | | | | | | | | | | | | | | Some use cases are appearing where salvaging is needed that does not correspond to an instruction being deleted -- for example an instruction being sunk, or a Value not being available in a block being isel'd. Enable more fine grained control over how salavging occurs by splitting the logic into helper functions, separating things that are specific to working on DbgVariableIntrinsics from those specific to interpreting IR and building DIExpressions. Differential Revision: https://reviews.llvm.org/D57696 llvm-svn: 353156
* [X86][AVX] Attempt to share broadcasts of different widths (PR39454)Simon Pilgrim2019-02-051-0/+8
| | | | | | | | If we have broadcasts of different vector widths, keep the longest vector width and extract subvectors for the shorter vectors (which should be free). Differential Revision: https://reviews.llvm.org/D57663 llvm-svn: 353154
* [CGP] Add support for sinking operands to their users, if they are free.Florian Hahn2019-02-053-0/+158
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch improves code generation for some AArch64 ACLE intrinsics. It adds support to CGP to duplicate and sink operands to their user, if they can be folded into a target instruction, like zexts and sub into usubl. It adds a TargetLowering hook shouldSinkOperands, which looks at the operands of instructions to see if sinking is profitable. I decided to add a new target hook, as for the sinking to be profitable, at least on AArch64, we have to look at multiple operands of an instruction, instead of looking at the users of a zext for example. The sinking is done in CGP, because it works around an instruction selection limitation. If instruction selection is not limited to a single basic block, this patch should not be needed any longer. Alternatively this could be done in the LoopSink pass, which tries to undo LICM for instructions in blocks that are not executed frequently. Note that we do not force the operands to sink to have a single user, because we duplicate them before sinking. Therefore this is only desirable if they really can be done for free. Additionally we could consider the impact on live ranges later on. This should fix https://bugs.llvm.org/show_bug.cgi?id=40025. As for performance, we have internal code that uses intrinsics and can be speed up by 10% by this change. Reviewers: SjoerdMeijer, t.p.northover, samparker, efriedma, RKSimon, spatel Reviewed By: samparker Differential Revision: https://reviews.llvm.org/D57377 llvm-svn: 353152
* [ARM GlobalISel] Support G_GEP for Thumb2Diana Picus2019-02-052-3/+3
| | | | | | Same as ARM, but use a different opcode in the instruction selection. llvm-svn: 353151
* [NFC] fix trivial typos in commentsHiroshi Inoue2019-02-058-13/+13
| | | | llvm-svn: 353147
* [DAG] BaseIndexOffset: FrameIndexSDNodes with the same FrameIndex compare equal.Clement Courbet2019-02-051-5/+9
| | | | | | | | | | | | Reviewers: niravd Subscribers: arphaman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57692 llvm-svn: 353143
* [X86] Connect the default fpsr and dirflag clobbers in inline assembly to ↵Craig Topper2019-02-052-1/+9
| | | | | | | | | | | | | | | | | | | | | the registers we have defined for them. Summary: We don't currently map these constraints to physical register numbers so they don't make it to the MachineIR representation of inline assembly. This could have problems for proper dependency tracking in the machine schedulers though I don't have a test case that shows that. Reviewers: rnk Reviewed By: rnk Subscribers: eraman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57641 llvm-svn: 353141
* [LSR] Check SCEV on isZero() after extend. PR40514Max Kazantsev2019-02-051-3/+21
| | | | | | | | | | | | | | | | | | | | | When LSR first adds SCEVs to BaseRegs, it only does it if `isZero()` has returned false. In the end, in invocation of `InsertFormula`, it asserts that all values there are still not zero constants. However between these two points, it makes some transformations, in particular extends them to wider type. SCEV does not give us guarantee that if `S` is not a constant zero, then `sext(S)` is also not a constant zero. It might have missed some optimizing transforms when it was calculating `S` and then made them when it took `sext`. For example, it may happen if previously optimizing transforms were limited by depth or somehow else. This patch adds a bailout when we may end up with a zero SCEV after extension. Differential Revision: https://reviews.llvm.org/D57565 Reviewed By: samparker llvm-svn: 353136
* [SamplePGO] More pipeline changes when flattened profile used in ThinLTO ↵Teresa Johnson2019-02-051-20/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | postlink Summary: Follow on to D54819/r351476. We also don't need to perform extra InstCombine pass when we aren't loading the sample profile in the ThinLTO backend because we have a flattened sample profile. Additionally, for consistency and clarity, when we aren't reloading the sample profile, perform ICP in the same location as non-sample PGO backends. To this end I have moved the ICP invocation for non-SamplePGO ThinLTO down into buildModuleSimplificationPipeline (partly addresses the FIXME where we were previously setting this up). Reviewers: wmi Subscribers: mehdi_amini, inglorion, eraman, steven_wu, dexonsmith, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57705 llvm-svn: 353135
* Fix narrowing issue from r353129Richard Trieu2019-02-051-1/+2
| | | | llvm-svn: 353134
* [WebAssembly] Fix indentation after adding IsCanonical property (NFC)Heejin Ahn2019-02-052-11/+11
| | | | llvm-svn: 353132
* [WebAssembly] Make disassembler always emit most canonical name.Wouter van Oortmerssen2019-02-054-11/+22
| | | | | | | | | | | | | | | | | | | | | Summary: There are a few instructions that all map to the same opcode, so when disassembling, we have to pick one. That was just the first one before (the except_ref variant in the case of "call"), now it is the one marked as IsCanonical in tablegen, or failing that, the shortest name (which is typically the "canonical" one). Also introduced a canonical "end" instruction for this purpose. Reviewers: dschuff, tlively Subscribers: sbc100, jgravelle-google, aheejin, llvm-commits, sunfish Tags: #llvm Differential Revision: https://reviews.llvm.org/D57713 llvm-svn: 353131
* [SamplePGO][NFC] Minor improvement to replace a temporary vector with aWei Mi2019-02-051-3/+2
| | | | | | | | brace-enclosed init list. Differential Revision: https://reviews.llvm.org/D57726 llvm-svn: 353129
* GlobalISel: Fix verifier crashing on non-register operandsMatt Arsenault2019-02-051-1/+6
| | | | | | Also correct the wording of error on subregisters. llvm-svn: 353128
* [WebAssembly] memory.copyThomas Lively2019-02-056-0/+66
| | | | | | | | | | | | Summary: Depends on D57495. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, hiraditya, sunfish Differential Revision: https://reviews.llvm.org/D57498 llvm-svn: 353127
* GlobalISel: Consolidate load/store legalizationMatt Arsenault2019-02-051-103/+14
| | | | | | | | | | The fewerElementsVectors implementation for load/stores handles the scalar reduction case just as well, so drop the redundant code in narrowScalar. This also introduces support for narrowing irregular size breakdowns for scalars. llvm-svn: 353125
* [DAGCombiner] Discard pointer info when combining extract_vector_elt of a ↵Craig Topper2019-02-051-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | vector load when the index isn't constant Summary: If the index isn't constant, this transform inserts a multiply and an add on the index to calculating the base pointer for a scalar load. But we still create a memory operand with an offset of 0 and the size of the scalar access. But the access is really to an unknown offset within the original access size. This can cause the machine scheduler to incorrectly calculate dependencies between this load and other accesses. In the case we saw, there was a 32 byte vector store that was split into two 16 byte stores, one with offset 0 and one with offset 16. The size of the memory operand for both was 16. The scheduler correctly detected the alias with the offset 0 store, but not the offset 16 store. This patch discards the pointer info so we don't incorrectly detect aliasing. I wasn't sure if we could keep using the original offset and size without risking some other transform on the load changing the size. I tried to reduce a test case, but there's still a lot of memory operations needed to get the scheduler to do the bad reordering. So it looked pretty fragile to maintain. Reviewers: efriedma Reviewed By: efriedma Subscribers: arphaman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57616 llvm-svn: 353124
* [SamplePGO] Minor efficiency improvement in samplePGO ICPTeresa Johnson2019-02-051-3/+3
| | | | | | | | | | | | | | | | | | | | Summary: When attaching prof metadata to promoted direct calls in SamplePGO mode, no need to construct and use a SmallVector to pass a single count to the ArrayRef parameter, we can simply use a brace-enclosed init list. This made a small but consistent improvement for a ThinLTO backend compile I was measuring. Reviewers: wmi Subscribers: mehdi_amini, dexonsmith, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57706 llvm-svn: 353123
* GlobalISel: Implement narrowScalar for selectMatt Arsenault2019-02-051-0/+53
| | | | | | | | | | Don't handle vector conditions. I think this can be merged in the future with fewerElementsVectorSelect, although this becomes slightly tricky with a vector condition. llvm-svn: 353122
* GlobalISel: Combine g_extract with g_merge_valuesMatt Arsenault2019-02-041-0/+1
| | | | | | | | | | | | | | Try to use the underlying source registers. This enables legalization in more cases where some irregular operations are widened and others narrowed. This seems to make the test_combines_2 AArch64 test worse, since the MERGE_VALUES has multiple uses. Since this should be required for legalization, a hasOneUse check is probably inappropriate (or maybe should only be used if the merge is legal?). llvm-svn: 353121
* Revert "[PATCH] [TargetLibraryInfo] Update run time support for Windows"Evandro Menezes2019-02-041-59/+53
| | | | | | This reverts accidental commit ff5527718d5d3b9966f6e8948866c0dc15ffcf3c. llvm-svn: 353118
* [PATCH] [TargetLibraryInfo] Update run time support for WindowsEvandro Menezes2019-02-041-53/+59
| | | | | | | | | | | | | It seems that the run time for Windows has changed and supports more math functions than before. Since LLVM requires at least VS2015, I assume that this is the run time that would be redistributed with programs built with Clang. Thus, I based this update on the header file `math.h` that accompanies it. This patch addresses the PR40541. Unfortunately, I have no access to a Windows development environment to validate it. llvm-svn: 353114
* GlobalISel: Enforce operand types for constantsMatt Arsenault2019-02-041-0/+23
| | | | | | | | A number of of tests were using imm operands, not cimm. Since CSE relies on the exact ConstantInt* pointer used, and implicit conversions are generally evil, also enforce the bitsize of the types. llvm-svn: 353113
* GlobalISel: Verify g_selectMatt Arsenault2019-02-041-24/+40
| | | | | | | Factor the common vector element consistency check many instructions need out, although this makes the error messages worse. llvm-svn: 353112
* MachineVerifier: Move verification of G_* instructions to functionMatt Arsenault2019-02-041-100/+117
| | | | llvm-svn: 353111
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