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* Return's chain should be matching either the chain produced by theEvan Cheng2006-02-011-1/+2
| | | | | | value or the chain going into the load. llvm-svn: 25863
* another testcase.Chris Lattner2006-02-011-0/+17
| | | | llvm-svn: 25862
* When folding a load into a return of SSE value, check the chain toEvan Cheng2006-02-011-2/+3
| | | | | | ensure the memory location has not been clobbered. llvm-svn: 25861
* Remove an item. It's done.Evan Cheng2006-02-011-21/+0
| | | | llvm-svn: 25860
* Be smarter about whether to store the SSE return value in memory. IfEvan Cheng2006-01-311-9/+16
| | | | | | it is already available in memory, do a fld directly from there. llvm-svn: 25859
* turning these into 'adds' would require extra copiesChris Lattner2006-01-311-7/+5
| | | | llvm-svn: 25858
* - Allow XMM load (for scalar use) to be folded into ANDP* and XORP*.Evan Cheng2006-01-316-26/+127
| | | | | | - Use XORP* to implement fneg. llvm-svn: 25857
* Remove entries on fabs and fneg. These are done.Evan Cheng2006-01-311-49/+0
| | | | llvm-svn: 25856
* Allow the specification of explicit alignments for constant pool entries.Evan Cheng2006-01-3110-32/+56
| | | | llvm-svn: 25855
* * Fix 80-column violationsChris Lattner2006-01-315-27/+67
| | | | | | | * Rename hasSSE -> hasSSE1 to avoid my continual confusion with 'has any SSE'. * Add inline asm constraint specification. llvm-svn: 25854
* add info about the inline asm register constraints for PPCChris Lattner2006-01-312-0/+60
| | | | llvm-svn: 25853
* Allow custom lowering of fabs. I forgot to check in this change whichEvan Cheng2006-01-311-1/+6
| | | | | | caused several test failures. llvm-svn: 25852
* add a missing break that caused a lot of failures last night :(Chris Lattner2006-01-311-0/+1
| | | | llvm-svn: 25851
* CodegenNate Begeman2006-01-311-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | bool %test(int %X) { %Y = seteq int %X, 13 ret bool %Y } as _test: addi r2, r3, -13 cntlzw r2, r2 srwi r3, r2, 5 blr rather than _test: cmpwi cr7, r3, 13 mfcr r2 rlwinm r3, r2, 31, 31, 31 blr This has very little effect on most code, but speeds up analyzer 23% and mason 11% llvm-svn: 25848
* okay, one moreChris Lattner2006-01-311-0/+2
| | | | llvm-svn: 25847
* another noteChris Lattner2006-01-311-1/+2
| | | | llvm-svn: 25846
* More notesChris Lattner2006-01-311-1/+15
| | | | llvm-svn: 25845
* another oneChris Lattner2006-01-311-0/+1
| | | | llvm-svn: 25844
* add a noteChris Lattner2006-01-311-0/+29
| | | | llvm-svn: 25843
* add conditional moves of float and double values on int/fp condition codes.Chris Lattner2006-01-311-6/+27
| | | | llvm-svn: 25842
* example nate pointed outChris Lattner2006-01-311-0/+33
| | | | llvm-svn: 25841
* treat conditional branches the same way as conditional moves (giving themChris Lattner2006-01-313-129/+17
| | | | | | an operand that contains the condcode), making things significantly simpler. llvm-svn: 25840
* compactify all of the integer conditional moves into one instruction that takesChris Lattner2006-01-314-166/+144
| | | | | | a CC as an operand. Much smaller, much happier. llvm-svn: 25839
* Add immediate forms of integer cmovsChris Lattner2006-01-311-6/+49
| | | | llvm-svn: 25838
* ShrinkifyChris Lattner2006-01-311-143/+86
| | | | llvm-svn: 25837
* Add the full complement of conditional moves of integer registers.Chris Lattner2006-01-311-7/+115
| | | | llvm-svn: 25834
* Compile this:Chris Lattner2006-01-311-21/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | void %X(int %A) { %C = setlt int %A, 123 ; <bool> [#uses=1] br bool %C, label %T, label %F T: ; preds = %0 call int %main( int 0 ) ; <int>:0 [#uses=0] ret void F: ; preds = %0 ret void } to this: X: save -96, %o6, %o6 subcc %i0, 122, %l0 bg .LBBX_2 ! F nop ... not this: X: save -96, %o6, %o6 sethi 0, %l0 or %g0, 1, %l1 subcc %i0, 122, %l2 bg .LBBX_4 ! nop .LBBX_3: ! or %g0, %l0, %l1 .LBBX_4: ! subcc %l1, 0, %l0 bne .LBBX_2 ! F nop llvm-svn: 25833
* Only insert an AND when converting from BR_COND to BRCC if needed.Chris Lattner2006-01-311-1/+3
| | | | llvm-svn: 25832
* Added custom lowering of fabsEvan Cheng2006-01-313-4/+49
| | | | llvm-svn: 25831
* add the 'lucas' optimizationChris Lattner2006-01-311-0/+25
| | | | llvm-svn: 25830
* I don't see why this optimization isn't safe, but it isn't, so disable itChris Lattner2006-01-311-1/+2
| | | | llvm-svn: 25829
* Another high-prio selection performance bugChris Lattner2006-01-311-0/+46
| | | | llvm-svn: 25828
* Handle physreg input/outputs. We now compile this:Chris Lattner2006-01-312-4/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | int %test_cpuid(int %op) { %B = alloca int %C = alloca int %D = alloca int %A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op) %Bv = load int* %B %Cv = load int* %C %Dv = load int* %D %x = add int %A, %Bv %y = add int %x, %Cv %z = add int %y, %Dv ret int %z } to this: _test_cpuid: sub %ESP, 16 mov DWORD PTR [%ESP], %EBX mov %EAX, DWORD PTR [%ESP + 20] cpuid mov DWORD PTR [%ESP + 8], %ECX mov DWORD PTR [%ESP + 12], %EBX mov DWORD PTR [%ESP + 4], %EDX mov %ECX, DWORD PTR [%ESP + 12] add %EAX, %ECX mov %ECX, DWORD PTR [%ESP + 8] add %EAX, %ECX mov %ECX, DWORD PTR [%ESP + 4] add %EAX, %ECX mov %EBX, DWORD PTR [%ESP] add %ESP, 16 ret ... note the proper register allocation. :) it is unclear to me why the loads aren't folded into the adds. llvm-svn: 25827
* more mumblingChris Lattner2006-01-311-0/+4
| | | | llvm-svn: 25826
* add some notesChris Lattner2006-01-311-0/+24
| | | | llvm-svn: 25825
* Don't generate complex sequence for SETOLE, SETOLT, SETULT, and SETUGT. FlipEvan Cheng2006-01-301-69/+32
| | | | | | | the order of the compare operands and generate SETOGT, SETOGE, SETUGE, and SETULE instead. llvm-svn: 25824
* Print the most trivial inline asms.Chris Lattner2006-01-301-1/+12
| | | | llvm-svn: 25822
* Fix a bug in my legalizer reworking that caused the X86 backend to not getChris Lattner2006-01-301-2/+1
| | | | | | | a chance to custom legalize setcc, which broke a bunch of C++ Codes. Testcase here: CodeGen/X86/2006-01-30-LongSetcc.ll llvm-svn: 25821
* Fix FP constants, and the SparcV8/2006-01-22-BitConvertLegalize.ll failure ↵Chris Lattner2006-01-301-0/+3
| | | | | | from last night llvm-svn: 25819
* i64 -> f32, f32 -> i64 and some clean up.Evan Cheng2006-01-301-31/+27
| | | | llvm-svn: 25818
* Always use FP stack instructions to perform i64 to f64 as well as f64 to i64Evan Cheng2006-01-303-17/+64
| | | | | | conversions. SSE does not have instructions to handle these tasks. llvm-svn: 25817
* Revamp the ICC/FCC reading instructions to be parameterized in terms of theChris Lattner2006-01-302-71/+212
| | | | | | | SPARC condition codes, not in terms of the DAG condcodes. This allows us to write nice clean patterns for cmovs/branches. llvm-svn: 25815
* Compile:Chris Lattner2006-01-302-16/+27
| | | | | | | | | | | | | | | | | | | | | | | | uint %test(uint %X) { %Y = call uint %llvm.ctpop.i32(uint %X) ret uint %Y } to: test: save -96, %o6, %o6 sll %i0, 0, %l0 popc %l0, %i0 restore %g0, %g0, %g0 retl nop instead of to 40 logical ops. Note the shift-by-zero that clears the top part of the 64-bit V9 register. Testcase here: CodeGen/SparcV8/ctpop.ll llvm-svn: 25814
* If the target has V9 instructions, this pass is a noop, don't botherChris Lattner2006-01-301-8/+16
| | | | | | running it. llvm-svn: 25811
* When in v9 mode, emit fabsd/fnegd/fmovdChris Lattner2006-01-301-8/+30
| | | | llvm-svn: 25810
* First step towards V9 instructions in the V8 backend, two conditional moveChris Lattner2006-01-303-7/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | patterns. This allows emission of this code: t1: save -96, %o6, %o6 subcc %i0, %i1, %l0 move %icc, %i0, %i2 or %g0, %i2, %i0 restore %g0, %g0, %g0 retl nop instead of this: t1: save -96, %o6, %o6 subcc %i0, %i1, %l0 be .LBBt1_2 ! nop .LBBt1_1: ! or %g0, %i2, %i0 .LBBt1_2: ! restore %g0, %g0, %g0 retl nop for this: int %t1(int %a, int %b, int %c) { %tmp.2 = seteq int %a, %b %tmp3 = select bool %tmp.2, int %a, int %c ret int %tmp3 } llvm-svn: 25809
* Two changes:Chris Lattner2006-01-301-0/+11
| | | | | | | 1. Default to having V9 instructions, instead of just V8. 2. unless -enable-sparc-v9-insts is passed, disable V9 (for use with llcbeta) llvm-svn: 25807
* When lowering SELECT_CC, see if the input is a lowered SETCC. If so, foldChris Lattner2006-01-301-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | the two operations together. This allows us to compile this: void %two(int %a, int* %b) { %tmp.2 = seteq int %a, 0 %tmp.0.0 = select bool %tmp.2, int 10, int 20 store int %tmp.0.0, int* %b ret void } into: two: save -96, %o6, %o6 or %g0, 20, %l0 or %g0, 10, %l1 subcc %i0, 0, %l2 be .LBBtwo_2 ! entry nop .LBBtwo_1: ! entry or %g0, %l0, %l1 .LBBtwo_2: ! entry st %l1, [%i1] restore %g0, %g0, %g0 retl nop instead of: two: save -96, %o6, %o6 sethi 0, %l0 or %g0, 1, %l1 or %g0, 20, %l2 or %g0, 10, %l3 subcc %i0, 0, %l4 be .LBBtwo_2 ! entry nop .LBBtwo_1: ! entry or %g0, %l0, %l1 .LBBtwo_2: ! entry subcc %l1, 0, %l0 bne .LBBtwo_4 ! entry nop .LBBtwo_3: ! entry or %g0, %l2, %l3 .LBBtwo_4: ! entry st %l3, [%i1] restore %g0, %g0, %g0 retl nop llvm-svn: 25806
* Add AddSymbol() method to DynamicLibrary to work around Windows limitationJeff Cohen2006-01-302-0/+21
| | | | | | | of being unable to search for symbols in an EXE. It will also allow other existing hacks to be improved. llvm-svn: 25805
* don't insert an and node if it isn't needed here, this can prevent foldingChris Lattner2006-01-301-1/+3
| | | | | | of lowered target nodes. llvm-svn: 25804
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