summaryrefslogtreecommitdiffstats
path: root/llvm/lib
diff options
context:
space:
mode:
authorChris Lattner <sabre@nondot.org>2006-01-31 05:04:52 +0000
committerChris Lattner <sabre@nondot.org>2006-01-31 05:04:52 +0000
commite9721b29849d16ce20c8839376413fcabed46c38 (patch)
tree8717e44b366ae72108e60ec7c5cd686ea8995fdf /llvm/lib
parent2dd217b88f25a7acdd60f468a535be8971453671 (diff)
downloadbcm5719-llvm-e9721b29849d16ce20c8839376413fcabed46c38.tar.gz
bcm5719-llvm-e9721b29849d16ce20c8839376413fcabed46c38.zip
Only insert an AND when converting from BR_COND to BRCC if needed.
llvm-svn: 25832
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp4
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 79037d3020f..f09fa625006 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -703,7 +703,9 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
} else {
// Make sure the condition is either zero or one. It may have been
// promoted from something else.
- Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
+ unsigned NumBits = MVT::getSizeInBits(Tmp2.getValueType());
+ if (!TLI.MaskedValueIsZero(Tmp2, (~0ULL >> (64-NumBits))^1))
+ Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
DAG.getCondCode(ISD::SETNE), Tmp2,
OpenPOWER on IntegriCloud