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* [X86][X87] Tag x87 float compare instructions scheduler classesSimon Pilgrim2017-12-081-11/+15
| | | | llvm-svn: 320189
* AMDGPU: Set IntrReadMem on memtime intrinsicsMatt Arsenault2017-12-081-5/+2
| | | | llvm-svn: 320188
* AMDGPU: image_getlod and image_getresinfo do not read memoryMatt Arsenault2017-12-082-13/+40
| | | | llvm-svn: 320187
* AMDGPU: Preserve MMO in adjustWritemaskMatt Arsenault2017-12-081-0/+2
| | | | | | | | Follow up to r319705. Currently the MMO is produced after this in the custom inserter, so this doesn't change anything yet. llvm-svn: 320186
* Revert r320104: infinite loop profiling bug fixXinliang David Li2017-12-083-36/+38
| | | | | | | | | | | Causes unexpected memory issue with New PM this time. The new PM invalidates BPI but not BFI, leaving the reference to BPI from BFI invalid. Abandon this patch. There is a more general solution which also handles runtime infinite loop (but not statically). llvm-svn: 320180
* [JumpThreading] Minor comment cleanup. NFC. (test commit)Brian M. Rzycki2017-12-081-2/+2
| | | | llvm-svn: 320179
* [X86][MPX] Tag TSX/HLE/SGX instructions scheduler classesSimon Pilgrim2017-12-082-0/+7
| | | | | | Currently tagged these as system instructions. llvm-svn: 320177
* AMDGPU: Report Arg's Value name in metadata if kernel_arg_name metadata is ↵Konstantin Zhuravlyov2017-12-081-0/+2
| | | | | | | | not available Differential Revision: https://reviews.llvm.org/D40924 llvm-svn: 320176
* Reverting r320166 to fix test failures.Michael Trent2017-12-081-23/+1
| | | | llvm-svn: 320174
* [X86][MPX] Tag MPX instructions scheduler classesSimon Pilgrim2017-12-082-14/+19
| | | | | | Currently tagged these as system instructions, once we have uses for them (ASAN?) and they are faster we will need to improve on this. llvm-svn: 320173
* [x86] use hasAVX2() rather than hasInt256(); NFCSanjay Patel2017-12-081-3/+3
| | | | | | | | These are aliases, but the thing we're checking here is that the target has vpsllv*, not that the data type is 256-bit. Those instructions exist for 128-bit vectors too...but sadly, not for all element sizes. llvm-svn: 320170
* [X86] Tag move immediate instructions scheduler classesSimon Pilgrim2017-12-082-20/+29
| | | | llvm-svn: 320169
* Updated llvm-objdump to display local relocations in Mach-O binariesMichael Trent2017-12-081-1/+23
| | | | | | | | | | | | | | | | | | | | Summary: llvm-objdump's Mach-O parser was updated in r306037 to display external relocations for MH_KEXT_BUNDLE file types. This change extends the Macho-O parser to display local relocations for MH_PRELOAD files. When used with the -macho option relocations will be displayed in a historical format. rdar://35778019 Reviewers: enderby Reviewed By: enderby Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D40867 llvm-svn: 320166
* [X86][SHA] Tag SHA instructions scheduler classesSimon Pilgrim2017-12-081-11/+22
| | | | | | Put these under VecIMul itinerary classes for now - seems to be a good average value llvm-svn: 320161
* [X86] Tag VIA PadLock crypto instructions scheduler classesSimon Pilgrim2017-12-081-1/+3
| | | | llvm-svn: 320159
* [X86] Tag PKU/INVPCID/RDPID/SMAP/SMX/PTWRITE system instructions scheduler ↵Simon Pilgrim2017-12-082-16/+36
| | | | | | classes llvm-svn: 320158
* [InstCombine] PR35354: Convert store(bitcast, load bitcast (select (Cond, ↵Alexey Bataev2017-12-081-1/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | &V1, &V2)) --> store (, load (select(Cond, load &V1, load &V2))) Summary: If we have the code like this: ``` float a, b; a = std::max(a ,b); ``` it is converted into something like this: ``` %call = call dereferenceable(4) float* @_ZSt3maxIfERKT_S2_S2_(float* nonnull dereferenceable(4) %a.addr, float* nonnull dereferenceable(4) %b.addr) %1 = bitcast float* %call to i32* %2 = load i32, i32* %1, align 4 %3 = bitcast float* %a.addr to i32* store i32 %2, i32* %3, align 4 ``` After inlinning this code is converted to the next: ``` %1 = load float, float* %a.addr %2 = load float, float* %b.addr %cmp.i = fcmp fast olt float %1, %2 %__b.__a.i = select i1 %cmp.i, float* %a.addr, float* %b.addr %3 = bitcast float* %__b.__a.i to i32* %4 = load i32, i32* %3, align 4 %5 = bitcast float* %arrayidx to i32* store i32 %4, i32* %5, align 4 ``` This pattern is not recognized as minmax pattern. Patch solves this problem by converting sequence ``` store (bitcast, (load bitcast (select ((cmp V1, V2), &V1, &V2)))) ``` to a sequence ``` store (,load (select((cmp V1, V2), &V1, &V2))) ``` After this the code is recognized as minmax pattern. Reviewers: RKSimon, spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D40304 llvm-svn: 320157
* [X86][AVX512] Tag CLWB instruction to CLFLUSH/PREFETCH scheduler classSimon Pilgrim2017-12-081-3/+2
| | | | llvm-svn: 320156
* [X86][AVX512] Tag AVX512_512_SEXT_MASK_* instructions scheduler classesSimon Pilgrim2017-12-081-1/+1
| | | | | | Match VPTERNLOG which these pseudos will eventually alias to llvm-svn: 320154
* [AMDGPU] add labels to +DumpCode outputTim Renouf2017-12-082-4/+29
| | | | | | | | | | | | | | Summary: +DumpCode is a hack to embed disassembly in the ELF file. This commit fixes it to include labels, to make it slightly more useful. Reviewers: arsenm, kzhuravl Subscribers: nhaehnle, timcorringham, dstuttard, llvm-commits, t-tye, yaxunl, wdng, kzhuravl Differential Revision: https://reviews.llvm.org/D40169 llvm-svn: 320146
* [NFC] Rename variable from Cond to Pred to make it more soundMax Kazantsev2017-12-081-12/+12
| | | | llvm-svn: 320144
* [SCEV] Fix predicate usage in computeExitLimitFromICmpMax Kazantsev2017-12-081-1/+2
| | | | | | | | | | | | | | | | | | | In this method, we invoke `SimplifyICmpOperands` which takes the `Cond` predicate by reference and may change it along with `LHS` and `RHS` SCEVs. But then we invoke `computeShiftCompareExitLimit` with Values from which the SCEVs have been derived, these Values have not been modified while `Cond` could be. One of possible outcomes of this is that we may falsely prove that an infinite loop ends within some finite number of iterations. In this patch, we save the original `Cond` and pass it along with original operands. This logic may be removed in future once `computeShiftCompareExitLimit` works with SCEVs instead of value operands. Reviewed By: sanjoy Differential Revision: https://reviews.llvm.org/D40953 llvm-svn: 320142
* [CodeGen] Move printing MO_MachineBasicBlock operands to MachineOperand::printFrancis Visoiu Mistrih2017-12-081-4/+2
| | | | | | | Work towards the unification of MIR and debug output by refactoring the interfaces. llvm-svn: 320141
* [CodeGen] Move printing MO_CImmediate operands to MachineOperand::printFrancis Visoiu Mistrih2017-12-082-5/+3
| | | | | | | Work towards the unification of MIR and debug output by refactoring the interfaces. llvm-svn: 320140
* [X86][Haswell]: Updating the scheduling information for the Haswell subtarget.Gadi Haber2017-12-081-797/+910
| | | | | | | | | | | | | | Updated the scheduling information for the Haswell subtarget with the following changes: Regrouped the instructions after adding appropriate load + store latencies. Added scheduling for missing instructions such as the GATHER instrs. The changes were made after revisiting the latencies impact of all memory uOps. Reviewers: RKSimon, zvi, craig.topper, apilipenko Differential Revision: https://reviews.llvm.org/D40021 Change-Id: Iaf6c1f5169add1552845a8a566af4e5a359217a7 llvm-svn: 320137
* [FuzzMutate] Correctly insert sinks and sources around invoke instructionsIgor Laevsky2017-12-081-1/+8
| | | | | | Differential Revision: https://reviews.llvm.org/D40840 llvm-svn: 320136
* [X86] Always consider inserting a vXi1 vector into the lsbs of a zero vector ↵Craig Topper2017-12-082-27/+104
| | | | | | | | | | | | to be legal during lowering. Add isel patterns to emit shifts. Previously we only allowed these through if the subvector came from a compare or test instruction which we would again check for during isel. With this change we only check for the compare and test instructions during isel and have fallback patterns that emit the shifts if needed. I noticed that in a lot of cases we don't actually see the compare during lowering and rely on an odd legalization of concat_vectors with a zero vector as the second argument. This keeps the concat_vectors around long enough for a later dag combine to expose the compare then we re-legalize the concat_vectors and catch the compare. llvm-svn: 320134
* [AArch64] Avoid SIMD interleaved store instruction for Exynos.Abderrazek Zaafrani2017-12-083-122/+469
| | | | | | | Replace interleaved store instructions by equivalent and more efficient instructions based on latency cost model. Https://reviews.llvm.org/D38196 llvm-svn: 320123
* Revert "[WebAssemby] Support main functions with alternate signatures."Derek Schuff2017-12-081-45/+1
| | | | | | | | | This reverts commit 959e37e669b0c3cfad4cb9f1f7c9261ce9f5e9ae. That commit doesn't handle the case where main is declared rather than defined, in particular the even-more special case where main is a prototypeless declaration (which is of course the one actually used by musl currently). llvm-svn: 320121
* [X86] Handle alls version of vXi1 insert_vector_elt with a constant index ↵Craig Topper2017-12-081-21/+22
| | | | | | | | | | | | without falling back to shuffles. We previously only supported inserting to the LSB or MSB where it was easy to zero to perform an OR to insert. This change effectively extracts the old value and the new value, xors them together and then xors that single bit with the correct location in the original vector. This will cancel out the old value in the first xor leaving the new value in the position. The way I've implemented this uses 3 shifts and two xors and uses an additional register. We can avoid the additional register at the cost of another shift. llvm-svn: 320120
* [X86] Fix indentation. NFCCraig Topper2017-12-081-2/+2
| | | | llvm-svn: 320119
* [PowerPC][asan] Update asan to handle changed memory layouts in newer kernelsBill Seurer2017-12-071-1/+1
| | | | | | | | | | | | | | | In more recent Linux kernels with 47 bit VMAs the layout of virtual memory for powerpc64 changed causing the address sanitizer to not work properly. This patch adds support for 47 bit VMA kernels for powerpc64 and fixes up test cases. https://reviews.llvm.org/D40907 There is an associated patch for compiler-rt. Tested on several 4.x and 3.x kernel releases. llvm-svn: 320109
* [DebugInfo] Fix register variables not showing up in pdb.Zachary Turner2017-12-071-0/+3
| | | | | | | | | | | | | Previously, when linking against libcmt from the MSVC runtime, lld-link /verbose would show "Ignoring unknown symbol record with kind 0x1006". It turns out this was because TypeIndexDiscovery did not handle S_REGISTER records, so these records were not getting properly remapped. Patch by: Alexnadre Ganea Differential Revision: https://reviews.llvm.org/D40919 llvm-svn: 320108
* [ModRefInfo] Make enum ModRefInfo an enum class [NFC].Alina Sbirlea2017-12-0712-127/+131
| | | | | | | | | | | | | | | Summary: Make enum ModRefInfo an enum class. Changes to ModRefInfo values should be done using inline wrappers. This should prevent future bit-wise opearations from being added, which can be more error-prone. Reviewers: sanjoy, dberlin, hfinkel, george.burgess.iv Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D40933 llvm-svn: 320107
* Temporarily revert "[PowerPC] Allow tail calls of fastcc functions from C ↵Eric Christopher2017-12-071-10/+5
| | | | | | | | | | CallingConv functions." It is causing sanitizer failures on llvm tests in a bootstrapped compiler. No bot link since it's currently down, but following up to get the bot up. This reverts commit r319218. llvm-svn: 320106
* [PGO] detect infinite loop and form MST properlyXinliang David Li2017-12-073-38/+36
| | | | | | Differential Revision: http://reviews.llvm.org/D40873 llvm-svn: 320104
* [MachineOutliner] Fix offset overflow checkJessica Paquette2017-12-071-4/+6
| | | | | | | | | | | | The offset overflow check before was incorrect. It would always give the correct result, but it was comparing the SCALED potential fixed-up offset against an UNSCALED minimum/maximum. As a result, the outliner was missing a bunch of frame setup/destroy instructions that ought to have been safe to outline. This fixes that, and adds an instruction to the .mir test that failed the old test. llvm-svn: 320090
* [AMDGPU] Revert "[AMDGPU] Add options for waitcnt pass debugging; add instr ↵Mark Searles2017-12-071-62/+8
| | | | | | | | | | | | | | count in debug output." Patch caused a buildbot failure; http://lab.llvm.org:8011/builders/lld-x86_64-darwin13/builds/15733/steps/build_Lld/logs/stdio : lib/Target/AMDGPU/SIInsertWaitcnts.cpp:396:11: error: private field 'InstCnt' is not used [-Werror,-Wunused-private-field] int32_t InstCnt = 0; ^ 1 error generated. " This reverts commit 71627f79010aafe74fdcba901bba28dd7caa0869. llvm-svn: 320086
* [AMDGPU] Add options for waitcnt pass debugging; add instr count in debug ↵Mark Searles2017-12-071-8/+62
| | | | | | | | | | | | | output. -amdgpu-waitcnt-forcezero={1|0} Force all waitcnt instrs to be emitted as s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -amdgpu-waitcnt-forceexp=<n> Force emit a s_waitcnt expcnt(0) before the first <n> instrs -amdgpu-waitcnt-forcelgkm=<n> Force emit a s_waitcnt lgkmcnt(0) before the first <n> instrs -amdgpu-waitcnt-forcevm=<n> Force emit a s_waitcnt vmcnt(0) before the first <n> instrs Differential Revision: https://reviews.llvm.org/D40091 llvm-svn: 320084
* [AMDGPU] Add GCNHazardRecognizer::checkInlineAsmHazards() and ↵Mark Searles2017-12-072-17/+64
| | | | | | | | GCNHazardRecognizer::checkVALUHazardsHelper(). checkInlineAsmHazards() checks INLINEASM for hazards that we particularly care about (so not exhaustive); this patch adds a check for INLINEASM that defs vregs that hold data-to-be stored by immediately preceding store of more than 8 bytes. If the instr were not within an INLINEASM, this scenario would be handled by checkVALUHazard(). Add checkVALUHazardsHelper(), which will be called by both checkVALUHazards() and checkInlineAsmHazards(). Differential Revision: https://reviews.llvm.org/D40098 llvm-svn: 320083
* [X86] Fix InsertBitToMaskVector to only issue KSHIFTS of native size so that ↵Craig Topper2017-12-071-7/+33
| | | | | | | | | | | | upper bits are properly zeroed. There's no v2i1 or v4i1 kshift, and v8i1 is only supported with AVXDQ. Isel has fake patterns to extend these types to native shifts, but makes no guarantees about the value of any bits shifted in when shifting right. This patch promotes the vector to a type that supports a native shift first and only allows inserting into the msb of a native sized shift. I've constructed this in a way that doesn't do the promotion if we're going to fallback to using a xmm/ymm/zmm shuffle. I think I have a plan to remove the shuffle fall back entirely. In which case we this can be simplified, but I wanted to fix the correctness issue first. llvm-svn: 320081
* [X86] Fix typo in variable name. NFCCraig Topper2017-12-071-4/+4
| | | | llvm-svn: 320080
* [X86] Make a couple helper lowering methods static.Craig Topper2017-12-072-7/+4
| | | | llvm-svn: 320079
* [X86] Replace tabs with spaces. NFCI.Simon Pilgrim2017-12-071-12/+12
| | | | llvm-svn: 320065
* [X86] Tag BMI/BMI2/TBM instructions scheduler classesSimon Pilgrim2017-12-071-16/+16
| | | | | | Put these under UNARY/BINOP ALU itinerary classes for now - seems to be a good average value llvm-svn: 320064
* [Hexagon] Generate HVX code for basic arithmetic operationsKrzysztof Parzyszek2017-12-074-30/+137
| | | | | | Handle and, or, xor, add, sub, mul for vectors of i8, i16, and i32. llvm-svn: 320063
* [CodeGen] Fix index when printing tied machine operandsFrancis Visoiu Mistrih2017-12-071-3/+3
| | | | llvm-svn: 320061
* [X86] Tag SALC instructions scheduler classSimon Pilgrim2017-12-071-2/+2
| | | | | | Treat these the same as LAHF/SAHF (although its not a x86_64 instruction) llvm-svn: 320055
* [X86][VMX] Tag VMX instructions scheduler classesSimon Pilgrim2017-12-072-21/+32
| | | | | | Tagged all as system instructions llvm-svn: 320053
* [X86] Tag LZCNT/TZCNT instructions scheduler classesSimon Pilgrim2017-12-072-18/+28
| | | | | | Tagged as IMUL instructions for a reasonable approximation (ALU tends to be a lot faster) - POPCNT is currently tagged as FAdd which I think should be replaced with IMUL as well llvm-svn: 320051
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