| Commit message (Collapse) | Author | Age | Files | Lines |
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The label does not have a '#' prefix. Add parsing and encoding tests.
llvm-svn: 136360
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identical.
llvm-svn: 136355
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llvm-svn: 136341
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The new EH is more simple in many respects. Mainly, we don't have to worry about
the "llvm.eh.exception" and "llvm.eh.selector" calls being in weird places.
llvm-svn: 136339
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to new vectors.
llvm-svn: 136338
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landingpad.
llvm-svn: 136329
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LLVM*AsmPrinter.
GenLibDeps.pl fails to detect vtable references. As this is the only
referenced symbol from LLVM*Desc to LLVM*AsmPrinter on optimized
builds, the algorithm that creates the list of libraries to be linked
into tools doesn't know about the dependency and sometimes places the
libraries on the wrong order, yielding error messages like this:
../../lib/libLLVMARMDesc.a(ARMMCTargetDesc.cpp.o): In function
`llvm::ARMInstPrinter::ARMInstPrinter(llvm::MCAsmInfo const&)':
ARMMCTargetDesc.cpp:(.text._ZN4llvm14ARMInstPrinterC1ERKNS_9MCAsmInfoE
[llvm::ARMInstPrinter::ARMInstPrinter(llvm::MCAsmInfo
const&)]+0x2a): undefined reference to `vtable for
llvm::ARMInstPrinter'
llvm-svn: 136328
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value.
llvm-svn: 136326
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* InvokeInst: Get the landingpad instruction associated with this invoke.
* LandingPadInst: A method to reserve extra space for clauses.
llvm-svn: 136325
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llvm-svn: 136324
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using vextractf128. This will reduce the number of issued instruction
for several avx codes.
llvm-svn: 136323
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them to match 256-bit scalar_to_vector+zext.
llvm-svn: 136322
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Take advantage that the 128-bit vpxor zeros the higher part and use it.
This also fixes PR10491
llvm-svn: 136321
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a convert pattern close to the instruction definition.
llvm-svn: 136320
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fence.
llvm-svn: 136319
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This takes the new 'resume' instruction and turns it into a direct jump to the
caller's landing pad code. The caller's landingpad instruction is merged with
the landingpad instructions of the callee. This is a bit rough and makes some
assumptions in how the code works. But it passes a simple test.
llvm-svn: 136313
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If true and 'model' parameter is not an absolute path, a temp directory will be prepended.
Make it true by default to match current behaviour.
llvm-svn: 136310
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the writeback operand always the first.
llvm-svn: 136295
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This can happen in cases where TableGen generated asm matcher cannot check
whether a register operand is in the right register class. e.g. mem operands.
rdar://8204588
llvm-svn: 136292
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llvm-mc gives an "invalid operand" error for instructions that take an unsigned
immediate which have the high bit set such as:
pblendw $0xc5, %xmm2, %xmm1
llvm-mc treats all x86 immediates as signed values and range checks them.
A small number of x86 instructions use the imm8 field as a set of bits.
This change only changes those instructions and where the high bit is not
ignored. The others remain unchanged.
llvm-svn: 136287
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Use range checked immediate operands for instructions. Add tests.
llvm-svn: 136285
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llvm-svn: 136283
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llvm-svn: 136278
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Fix parsing of the 's' suffix for the mnemonic. Add tests.
llvm-svn: 136277
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llvm-svn: 136275
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Fix parsing of the 's' suffix for the mnemonic. Add tests.
llvm-svn: 136274
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llvm-svn: 136269
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Encode the width operand as it encodes in the instruction, which simplifies
the disassembler and the encoder, by using the imm1_32 operand def. Add a
diagnostic for the context-sensitive constraint that the width must be in
the range [1,32-lsb].
llvm-svn: 136264
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register-addend and immediate-addend versions. Temporarily XFAIL the asm parsing tests for these instructions.
llvm-svn: 136255
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This adds the new instructions 'landingpad' and 'resume'.
llvm-svn: 136253
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Assembly parser handling for extend instruction rotate operands. Add tests
for the sign extend instructions.
llvm-svn: 136252
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llvm-svn: 136250
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code, and all x86 processors will honor the required semantics.
llvm-svn: 136249
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llvm-svn: 136229
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Refactor the rest of the extend instructions to not artificially distinguish
between a rotate of zero and a rotate of any other value. Replace the by-zero
versions with Pat<>'s for ISel.
llvm-svn: 136226
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Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not
have an 'r' and an 'r_rot' version, but just a single version with a rotate
that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version.
llvm-svn: 136225
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llvm-svn: 136222
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llvm-svn: 136221
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llvm-svn: 136218
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C++0x.
llvm-svn: 136211
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llvm-svn: 136206
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llvm-svn: 136205
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llvm-svn: 136202
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llvm-svn: 136201
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usage of the shuffle bitmask. Both work in 128-bit lanes without
crossing, but in the former the mask of the high part is the same
used by the low part while in the later both lanes have independent
masks. Handle this properly and and add support for vpermilpd.
llvm-svn: 136200
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llvm-svn: 136199
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instructions it doesn't know about (like the atomic instructions I'm adding).
llvm-svn: 136198
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llvm-svn: 136197
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chunks of consequtive instructions. But, there is not any way to describe this in .debug_inline accelerator table used by gdb. However, describe non contiguous ranges of inlined function body appropriately using AT_range of DW_TAG_inlined_subroutine debug info entry.
llvm-svn: 136196
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When splitting global live ranges, it is now possible to split for
multiple destination intervals at once. Previously, we only had the main
and stack intervals.
Each edge bundle is assigned to a split candidate, and splitAroundRegion
will insert copies between the candidate intervals and the stack
interval as needed.
The multi-way splitting is used to split around compact regions when
enabled with -compact-regions. The best candidate register still gets
all the bundles it wants, but everything outside the main interval is
first split around compact regions before we create single-block
intervals.
Compact region splitting still causes some regressions, so it is not
enabled by default.
llvm-svn: 136186
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