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* Fix -Wreturn-type warning. NFC.Michael Liao2019-07-161-0/+1
| | | | llvm-svn: 366251
* AMDGPU/GlobalISel: Fix selection of private storesMatt Arsenault2019-07-161-6/+7
| | | | llvm-svn: 366249
* AMDGPU/GlobalISel: Select private loadsMatt Arsenault2019-07-163-1/+147
| | | | llvm-svn: 366248
* AMDGPU/GlobalISel: Select flat storesMatt Arsenault2019-07-161-2/+4
| | | | llvm-svn: 366246
* AMDGPU: Add register classes to flat store patternsMatt Arsenault2019-07-161-25/+25
| | | | | | | For some reason GlobalISelEmitter needs register classes to import these, although it works for the load patterns. llvm-svn: 366242
* [IndVars] Speculative fix for an assertion failure seen in botsPhilip Reames2019-07-161-1/+6
| | | | | | I don't have an IR sample which is actually failing, but the issue described in the comment is theoretically possible, and should be guarded against even if there's a different root cause for the bot failures. llvm-svn: 366241
* AMDGPU: Replace store PatFragsMatt Arsenault2019-07-162-14/+34
| | | | | | Convert the easy cases to formats understood for GlobalISel. llvm-svn: 366240
* AMDGPU/GlobalISel: Select flat loadsMatt Arsenault2019-07-167-56/+102
| | | | | | | | Now that the patterns use the new PatFrag address space support, the only blocker to importing most load patterns is the addressing mode complex patterns. llvm-svn: 366237
* Teach `llvm-pdbutil pretty -native` about `-injected-sources`Nico Weber2019-07-165-11/+247
| | | | | | | | | `pretty -native -injected-sources -injected-source-content` works with this patch, and produces identical output to the dia version. Differential Revision: https://reviews.llvm.org/D64428 llvm-svn: 366236
* [AMDGPU] Optimize atomic max/minJay Foad2019-07-161-36/+141
| | | | | | | | | | | | | | | | Summary: Extend the atomic optimizer to handle signed and unsigned max and min operations, as well as add and subtract. Reviewers: arsenm, sheredom, critson, rampitec Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, jfb, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64328 llvm-svn: 366235
* AMDGPU: Redefine load PatFragsMatt Arsenault2019-07-164-76/+105
| | | | | | | Rewrite PatFrags using the new PatFrag address space matching in tablegen. These will now work with both SelectionDAG and GlobalISel. llvm-svn: 366234
* [AMDGPU] Add the adjusted FP as a livein register.Michael Liao2019-07-163-34/+41
| | | | | | | | | | | | Reviewers: arsenm, rampitec Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64145 llvm-svn: 366223
* [Strict FP] Allow more relaxed schedulingUlrich Weigand2019-07-161-10/+21
| | | | | | | | | | | | | | Reimplement scheduling constraints for strict FP instructions in ScheduleDAGInstrs::buildSchedGraph to allow for more relaxed scheduling. Specifially, allow one strict FP instruction to be scheduled across another, as long as it is not moved across any global barrier. Differential Revision: https://reviews.llvm.org/D64412 Reviewed By: cameron.mcinally llvm-svn: 366222
* [Remarks] Simplify and refactor the RemarkParser interfaceFrancis Visoiu Mistrih2019-07-166-415/+338
| | | | | | | | | | | | | | | | | | | | Before, everything was based on some kind of type erased parser implementation which container a lot of boilerplate code when multiple formats were to be supported. This simplifies it by: * the remark now owns its arguments * *always* returning an error from the implementation side * working around the way the YAML parser reports errors: catch them through callbacks and re-insert them in a proper llvm::Error * add a CParser wrapper that is used when implementing the C API to avoid cluttering the C++ API with useless state * LLVMRemarkParserGetNext now returns an object that needs to be released to avoid leaking resources * add a new API to dispose of a remark entry: LLVMRemarkEntryDispose llvm-svn: 366217
* [Remarks][NFC] Combine ParserFormat and SerializerFormatFrancis Visoiu Mistrih2019-07-167-37/+58
| | | | | | It's useless to have both. llvm-svn: 366216
* [ADCE] Fix non-deterministic behaviour due to iterating over a pointer set.Amara Emerson2019-07-161-3/+8
| | | | | | | | Original patch by Yann Laigle-Chapuy Differential Revision: https://reviews.llvm.org/D64785 llvm-svn: 366215
* [DAGCombiner] fold (addcarry (xor a, -1), b, c) -> (subcarry b, a, !c) and ↵Amaury Sechet2019-07-161-16/+28
| | | | | | | | | | | | | | | | | | | flip carry. Summary: As per title. DAGCombiner only mathes the special case where b = 0, this patches extends the pattern to match any value of b. Depends on D57302 Reviewers: hfinkel, RKSimon, craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59208 llvm-svn: 366214
* AMDGPU/GlobalISel: Fix test failures in release buildMatt Arsenault2019-07-162-3/+6
| | | | | | | | | | | | Apparently the check for legal instructions during instruction select does not happen without an asserts build, so these would successfully select in release, and fail in debug. Make s16 and/or/xor legal. These can just be selected directly to the 32-bit operation, as is already done in SelectionDAG, so just make them legal. llvm-svn: 366210
* [AArch64] Implement __jcvt intrinsic from Armv8.3-AKyrylo Tkachov2019-07-161-1/+3
| | | | | | | | | | | | | | | | The jcvt intrinsic defined in ACLE [1] is available when ARM_FEATURE_JCVT is defined. This change introduces the AArch64 intrinsic, wires it up to the instruction and a new clang builtin function. The __ARM_FEATURE_JCVT macro is now defined when an Armv8.3-A or higher target is used. I've implemented the target detection logic in Clang so that this feature is enabled for architectures from armv8.3-a onwards (so -march=armv8.4-a also enables this, for example). make check-all didn't show any new failures. [1] https://developer.arm.com/docs/101028/latest/data-processing-intrinsics Differential Revision: https://reviews.llvm.org/D64495 llvm-svn: 366197
* [NFC] Test commit: add full stop at end of commentKyrylo Tkachov2019-07-161-1/+1
| | | | llvm-svn: 366195
* [DWARF] Fix the reserved values for unit length in DWARFDebugLine.Igor Kudrin2019-07-161-2/+2
| | | | | | | | | The DWARF3 documentation had inconsistency concerning the reserved range for unit length values. The issue was fixed in DWARF4. Differential Revision: https://reviews.llvm.org/D64622 llvm-svn: 366190
* [DWARF] Fix an incorrect format specifier.Igor Kudrin2019-07-161-1/+1
| | | | | | | | This adjusts the format specifier because PCOffset is uint16_t. Differential Revision: https://reviews.llvm.org/D64620 llvm-svn: 366189
* [DWARF] Simplify DWARFAttribute. NFC.Igor Kudrin2019-07-161-2/+2
| | | | | | | | | The first argument in the constructor was ignored, and the remaining arguments were always passed as their defaults. Differential Revision: https://reviews.llvm.org/D64407 llvm-svn: 366188
* [X86] In combineStore, don't convert v2f32 load/store pairs to f64 loads/stores.Craig Topper2019-07-161-3/+2
| | | | | | | Type legalization can take care of this. This gives DAG combine a little more time with the original types. llvm-svn: 366182
* [RISCV] Match GNU tools canonical JALR and add aliasesAlex Bradbury2019-07-161-7/+18
| | | | | | | | | | | | The canonical GNU form of JALR resembles a load/store instruction rather than placing the immediate offset as a separate argument, so match this behaviour. Also add parser-only aliases for the three-operand form, and add other shorter aliases also emitted by GNU tools. Differential Revision: https://reviews.llvm.org/D55277 Patch by James Clarke. llvm-svn: 366179
* Fix parameter name comments using clang-tidy. NFC.Rui Ueyama2019-07-1636-66/+66
| | | | | | | | | | | | | | | | | | | | | This patch applies clang-tidy's bugprone-argument-comment tool to LLVM, clang and lld source trees. Here is how I created this patch: $ git clone https://github.com/llvm/llvm-project.git $ cd llvm-project $ mkdir build $ cd build $ cmake -GNinja -DCMAKE_BUILD_TYPE=Debug \ -DLLVM_ENABLE_PROJECTS='clang;lld;clang-tools-extra' \ -DCMAKE_EXPORT_COMPILE_COMMANDS=On -DLLVM_ENABLE_LLD=On \ -DCMAKE_C_COMPILER=clang -DCMAKE_CXX_COMPILER=clang++ ../llvm $ ninja $ parallel clang-tidy -checks='-*,bugprone-argument-comment' \ -config='{CheckOptions: [{key: StrictMode, value: 1}]}' -fix \ ::: ../llvm/lib/**/*.{cpp,h} ../clang/lib/**/*.{cpp,h} ../lld/**/*.{cpp,h} llvm-svn: 366177
* [RISCV] Avoid overflow when determining number of nops for code alignAlex Bradbury2019-07-161-2/+6
| | | | | | | | | | | | RISCVAsmBackend::shouldInsertExtraNopBytesForCodeAlign() assumed that the align specified would be greater than or equal to the minimum nop length, but that is not always the case - for example if a user specifies ".align 0" in assembly. Differential Revision: https://reviews.llvm.org/D63274 Patch by Edward Jones. llvm-svn: 366176
* [RISCV] Fix a potential issue in shouldInsertFixupForCodeAlign()Alex Bradbury2019-07-161-4/+3
| | | | | | | | | | | The bool result of shouldInsertExtraNopBytesForCodeAlign() is not checked but the returned nop count is unconditionally read even though it could be uninitialized. Differential Revision: https://reviews.llvm.org/D63285 Patch by Edward Jones. llvm-svn: 366175
* [RISCV][NFC] Split PseudoCALL pattern out from instructionAlex Bradbury2019-07-161-2/+2
| | | | | | | | | | | | | Since PseudoCALL defines AsmString, it can be generated from assembly, and so code-gen patterns should be defined separately to be consistent with the style of the RISCV backend. Other pseudo-instructions exist that have code-gen patterns defined directly, but these instructions are purely for code-gen and cannot be written in assembly. Differential Revision: https://reviews.llvm.org/D64012 Patch by James Clarke. llvm-svn: 366174
* [RISCV][NFC] Fix HasStedExtA -> HasStdExtA typo in commentAlex Bradbury2019-07-161-1/+1
| | | | | | | Differential Revision: https://reviews.llvm.org/D64011 Patch by James Clarke. llvm-svn: 366173
* [RISCV] Make RISCVELFObjectWriter::getRelocType check IsPCRelAlex Bradbury2019-07-161-25/+36
| | | | | | | | | | | Previously, this function didn't check the IsPCRel argument. But doing so is a useful check for errors, and also seemingly necessary for FK_Data_4 (which we produce a R_RISCV_32_PCREL relocation for if IsPCRel). Other than R_RISCV_32_PCREL, this should be NFC. Future exception handling related patches will include tests that capture this behaviour. llvm-svn: 366172
* hwasan: Pad arrays with non-1 size correctly.Peter Collingbourne2019-07-161-5/+9
| | | | | | | | Spotted by eugenis. Differential Revision: https://reviews.llvm.org/D64783 llvm-svn: 366171
* AMDGPU: Avoid code predicates for extload PatFragsMatt Arsenault2019-07-165-48/+72
| | | | | | | | | | Use the MemoryVT field. This will be necessary for tablegen to automatically handle patterns for GlobalISel. Doesn't handle the d16 lo/hi patterns. Those are a special case since it involvess the custom node type. llvm-svn: 366168
* Re-land "[DebugInfo] Move function from line table to the prologue (NFC)"Jonas Devlieghere2019-07-161-34/+33
| | | | | | | | | | | | | | | | | In LLDB, when parsing type units, we don't need to parse the whole line table. Instead, we only need to parse the "support files" from the line table prologue. To make that possible, this patch moves the respective functions from the LineTable into the Prologue. Because I don't think users of the LineTable should have to know that these files come from the Prologue, I've left the original methods in place, and made them redirect to the LineTable. Differential revision: https://reviews.llvm.org/D64774 llvm-svn: 366164
* [InstructionSimplify] Apply sext/trunc after pointer strippingMichael Liao2019-07-161-0/+4
| | | | | | | | | | | | | | | | | Summary: - As the pointer stripping could trace through `addrspacecast` now, need to sext/trunc the offset to ensure it has the same width as the pointer after stripping. Reviewers: jdoerfert Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64768 llvm-svn: 366162
* Revert "[DebugInfo] Move function from line table to the prologue (NFC)"Jonas Devlieghere2019-07-161-33/+34
| | | | | | This broke LLD, which I didn't have enabled. llvm-svn: 366160
* [DebugInfo] Move function from line table to the prologue (NFC)Jonas Devlieghere2019-07-161-34/+33
| | | | | | | | | | | | | | | | | In LLDB, when parsing type units, we don't need to parse the whole line table. Instead, we only need to parse the "support files" from the line table prologue. To make that possible, this patch moves the respective functions from the LineTable into the Prologue. Because I don't think users of the LineTable should have to know that these files come from the Prologue, I've left the original methods in place, and made them redirect to the LineTable. Differential revision: https://reviews.llvm.org/D64774 llvm-svn: 366158
* Temporarily Revert "[SLP] Recommit: Look-ahead operand reordering heuristic."Eric Christopher2019-07-151-248/+46
| | | | | | | | | As there are some reported miscompiles with AVX512 and performance regressions in Eigen. Verified with the original committer and testcases will be forthcoming. This reverts commit r364964. llvm-svn: 366154
* Revert "[NewPM] Port Sancov"Leonard Chan2019-07-154-248/+118
| | | | | | This reverts commit 5652f35817f07b16f8b3856d594cc42f4d7ee29c. llvm-svn: 366153
* [X86] Teach convertToThreeAddress to handle SUB with immediateCraig Topper2019-07-152-7/+53
| | | | | | | | | | | | We mostly avoid sub with immediate but there are a couple cases that can create them. One is the add 128, %rax -> sub -128, %rax trick in isel. The other is when a SUB immediate gets created for a compare where both the flags and the subtract value is used. If we are unable to linearize the SelectionDAG to satisfy the flag user and the sub result user from the same instruction, we will clone the sub immediate for the two uses. The one that produces flags will eventually become a compare. The other will have its flag output dead, and could then be considered for LEA creation. I added additional test cases to add.ll to show the the sub -128 trick gets converted to LEA and a case where we don't need to convert it. This showed up in the current codegen for PR42571. Differential Revision: https://reviews.llvm.org/D64574 llvm-svn: 366151
* [WebAssembly] Add missing utility methods for exnref typeHeejin Ahn2019-07-152-0/+6
| | | | | | | | | | | | | | | | | | | | | | | Summary: This adds missing utility methods and copy instruction handling for `exnref` type and also adds tests. `tee` instruction tests are missing because `isTee` is currently only used in ExplicitLocals pass and testing that pass in mir requires serialization of stackified registers in mir files, which is a bit nontrivial because `MachineFunctionInfo` only has info of vreg numbers (which are large integers) but not the mir's register numbers. But this change is quite trivial anyway. Reviewers: tlively Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64705 llvm-svn: 366149
* [WebAssembly] Rename except_ref type to exnrefHeejin Ahn2019-07-1518-119/+114
| | | | | | | | | | | | | | | | | | | Summary: We agreed to rename `except_ref` to `exnref` for consistency with other reference types in https://github.com/WebAssembly/exception-handling/issues/79. This also renames WebAssemblyInstrExceptRef.td to WebAssemblyInstrRef.td in order to use the file for other reference types in future. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, hiraditya, sunfish, jfb, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64703 llvm-svn: 366145
* [WebAssembly] Assembler: support special floats: infinity / nanWouter van Oortmerssen2019-07-151-0/+25
| | | | | | | | | | | | | | | | | Summary: These are emitted as identifiers by the InstPrinter, so we should parse them as such. These could potentially clash with symbols of the same name, but that is out of our (the WebAssembly backend) control. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, aheejin, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64770 llvm-svn: 366139
* [AMDGPU] Enable merging m0 initializations.Austin Kerbow2019-07-151-15/+32
| | | | | | | | | | | | | | | | | | | | Summary: Enable hoisting and merging m0 defs that are initialized with the same immediate value. Fixes bug where removed instructions are not considered to interfere with other inits, and make sure to not hoist inits before block prologues. Reviewers: rampitec, arsenm Reviewed By: rampitec Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64766 llvm-svn: 366135
* [mips] Print BEQZL and BNEZL pseudo instructionsSimon Atanasyan2019-07-151-4/+4
| | | | | | One of the reasons - to be compatible with GNU tools. llvm-svn: 366133
* AMDGPU: Use standalone MUBUF load patternsMatt Arsenault2019-07-151-20/+37
| | | | | | | | | | | | | | | | | | We already do this for the flat and DS instructions, although it is certainly uglier and more verbose. This will allow using separate pattern definitions for extload and zextload. Currently we get away with using a single PatFrag with custom predicate code to check if the extension type is a zextload or anyextload. The generic mechanism the global isel emitter understands treats these as mutually exclusive. I was considering making the pattern emitter accept zextload or sextload extensions for anyextload patterns, but in global isel, the different extending loads have distinct opcodes, and there is currently no mechanism for an opcode matcher to try multiple (and there probably is very little need for one beyond this case). llvm-svn: 366132
* [LoopUnroll+LoopUnswitch] do not transform loops containing callbrNick Desaulniers2019-07-151-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: There is currently a correctness issue when unrolling loops containing callbr's where their indirect targets are being updated correctly to the newly created labels, but their operands are not. This manifests in unrolled loops where the second and subsequent copies of callbr instructions have blockaddresses of the label from the first instance of the unrolled loop, which would result in nonsensical runtime control flow. For now, conservatively do not unroll the loop. In the future, I think we can pursue unrolling such loops provided we transform the cloned callbr's operands correctly. Such a transform and its legalities are being discussed in: https://reviews.llvm.org/D64101 Link: https://bugs.llvm.org/show_bug.cgi?id=42489 Link: https://groups.google.com/forum/#!topic/clang-built-linux/z-hRWP9KqPI Reviewers: fhahn, hfinkel, efriedma Reviewed By: fhahn, hfinkel, efriedma Subscribers: efriedma, hiraditya, zzheng, dmgreen, llvm-commits, pirama, kees, nathanchance, E5ten, craig.topper, chandlerc, glider, void, srhines Tags: #llvm Differential Revision: https://reviews.llvm.org/D64368 llvm-svn: 366130
* AMDGPU/GlobalISel: Allow scalar s1 and/or/xorMatt Arsenault2019-07-151-6/+91
| | | | | | | | If a 1-bit value is in a 32-bit VGPR, the scalar opcodes set SCC to whether the result is 0. If the inputs are SCC, these can be copied to a 32-bit SGPR to produce an SCC result. llvm-svn: 366125
* ARM MTE stack sanitizer.Evgeniy Stepanov2019-07-159-1/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | Add "memtag" sanitizer that detects and mitigates stack memory issues using armv8.5 Memory Tagging Extension. It is similar in principle to HWASan, which is a software implementation of the same idea, but there are enough differencies to warrant a new sanitizer type IMHO. It is also expected to have very different performance properties. The new sanitizer does not have a runtime library (it may grow one later, along with a "debugging" mode). Similar to SafeStack and StackProtector, the instrumentation pass (in a follow up change) will be inserted in all cases, but will only affect functions marked with the new sanitize_memtag attribute. Reviewers: pcc, hctim, vitalybuka, ostannard Subscribers: srhines, mehdi_amini, javed.absar, kristof.beyls, hiraditya, cryptoad, steven_wu, dexonsmith, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D64169 llvm-svn: 366123
* AMDGPU/GlobalISel: Select G_AND/G_OR/G_XORMatt Arsenault2019-07-152-0/+66
| | | | llvm-svn: 366121
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