summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* [CodeGenPrepare][AddressingModeMatcher] Give up on type promotion if theQuentin Colombet2014-02-141-3/+33
| | | | | | | transformation does not bring any immediate benefits and introduce an illegal operation. llvm-svn: 201439
* TargetLowering: n * r where n > 2 should be an illegal addressing modeTom Stellard2014-02-141-0/+2
| | | | llvm-svn: 201433
* DebugInfo: Don't include the name of the CU file in the line table file list ↵David Blaikie2014-02-142-4/+2
| | | | | | | | | | | | | | | | | | | | when it's unneeded Recommitting r201380 (reverted in r201389) Recommitting r201351 and r201355 (reverted in r201351 and r201355) We weren't emitting the an empty (header only) line table when the line table was empty - this made the DWARF invalid (the compile unit would point to the zero-size debug_lines section where there should've been an empty line table but there was nothing at all). Fix that, and as a consequence this works around/addresses PR18809. Also, we emit a non-empty line table to workaround a darwin linker bug, so XFAILing on darwin too. Also, mark the test as 'REQUIRES: object-emission' because it does. llvm-svn: 201429
* Support DWARF discriminators in object streamer.Diego Novillo2014-02-143-3/+22
| | | | | | | | | | | | | | | Summary: This adds support for emitting DWARF path discriminator values in the object streamer. It also changes the DWARF dumper to show discriminator values in the line table output. Reviewers: echristo CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2794 llvm-svn: 201427
* This patch has two main functions:Reed Kotler2014-02-149-12/+453
| | | | | | | | | | | | | | | | | 1) Fix a specific bug when certain conversion functions are called in a program compiled as mips16 with hard float and the program is linked as c++. There are two libraries that are reversed in the link order with gcc/g++ and clang/clang++ for mips16 in this case and the proper stubs will then not be called. These stubs are normally handled in the Mips16HardFloat pass but in this case we don't know at that time that we need to generate the stubs. This must all be handled later in code generation and we have moved this functionality to MipsAsmPrinter. When linked as C (gcc or clang) the proper stubs are linked in from libc. 2) Set up the infrastructure to handle 90% of what is in the Mips16HardFloat pass in this new area of MipsAsmPrinter. This is a more logical place to handle this and we have known for some time that we needed to move the code later and not implement it using inline asm as we do now but it was not clear exactly where to do this and what mechanism should be used. Now it's clear to us how to do this and this patch contains the infrastructure to move most of this to MipsAsmPrinter but the actual moving will be done in a follow on patch. The same infrastructure is used to fix this current bug as described in #1. This change was requested by the list during the original putback of the Mips16HardFloat pass but was not practical for us do at that time. llvm-svn: 201426
* Trivial cleanup: reuse existing variable.Rafael Espindola2014-02-141-2/+1
| | | | | | | | Extracted while trying to understand http://llvm-reviews.chandlerc.com/D1764. Patch by Matt Arsenault. llvm-svn: 201425
* Generate the DWARF stack frame decode operations in the function prologue ↵Artyom Skrobov2014-02-145-39/+296
| | | | | | | | for ARM/Thumb functions. Patch by Keith Walker! llvm-svn: 201423
* [AArch64 NEON] Fix a bug to avoid using floating type as condition type in ↵Kevin Qin2014-02-141-11/+6
| | | | | | lowering SELECT_CC. llvm-svn: 201395
* Revert "DebugInfo: Don't include the name of the CU file in the line table ↵Eric Christopher2014-02-142-2/+4
| | | | | | | | file list when it's unneeded" This reverts commit r201380 for now while we investigate. llvm-svn: 201389
* Enable AArch64 NEON by default.Jiangning Liu2014-02-141-1/+1
| | | | llvm-svn: 201385
* [AArch64]Fix the assertion failure caused by "v1i1 SETCC" DAG node.Hao Liu2014-02-141-0/+90
| | | | | | As v1i1 is illegal, the type legalizer tries to scalarize such node. But if the type operands of SETCC is legal, the scalarization algorithm will cause an assertion failure. llvm-svn: 201381
* DebugInfo: Don't include the name of the CU file in the line table file list ↵David Blaikie2014-02-142-4/+2
| | | | | | | | | | | | | | when it's unneeded Recommitting r201351 and r201355 (reverted in r201351 and r201355) We weren't emitting the an empty (header only) line table when the line table was empty - this made the DWARF invalid (the compile unit would point to the zero-size debug_lines section where there should've been an empty line table but there was nothing at all). Fix that, and as a consequence this works around/addresses PR18809. llvm-svn: 201380
* Disable emission of aranges by default and add a command lineEric Christopher2014-02-141-1/+7
| | | | | | | option to enable again that will be matched with a commit to enable in clang. llvm-svn: 201378
* [X86] Don't mark movabsq as cheap-as-move - it isn't that cheap.Juergen Ributzka2014-02-141-3/+5
| | | | | | | | | A simple register copy on X86 is just 3 bytes, whereas movabsq is a 10 byte instruction. Marking movabsq as not beeing cheap will allow LICM to move it out of the loop and it also prevents unnecessary rematerializations if the value is needed in more than one register. llvm-svn: 201377
* Do more addrspacecast transforms that happen for bitcast.Matt Arsenault2014-02-141-6/+12
| | | | | | Makes addrspacecast (gep) do addrspacecast (gep) instead. llvm-svn: 201376
* R600/SI: Expand all v8[if]32 operationsTom Stellard2014-02-133-1/+37
| | | | llvm-svn: 201371
* R600/SI: Add a pattern for i32 anyextTom Stellard2014-02-131-2/+5
| | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 201370
* R600/SI: Completely Disable TypeRewriter on computeTom Stellard2014-02-131-3/+3
| | | | llvm-svn: 201369
* R600/SI: Split global vector loads with more than 4 elementsTom Stellard2014-02-131-3/+5
| | | | llvm-svn: 201368
* Use __literal16. It has been supported by the linker since 2005.Rafael Espindola2014-02-132-12/+6
| | | | llvm-svn: 201365
* Fix generation of 'isa' and 'discriminator' keywords.Diego Novillo2014-02-131-2/+2
| | | | | | | | | | | | | | | | | Summary: There should be a space before each of these two keywords to avoid generating invalid assembly files. NOTE: I could not find an obvious maintainers in CODE_OWNERS.TXT, but this seems related to debug info. Reviewers: echristo CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2791 llvm-svn: 201359
* Check that GlobalAliases don't have section or alignment.Rafael Espindola2014-02-132-0/+4
| | | | | | | An alias is always in the section of its aliasee and has the same alignment (since it has the same address). llvm-svn: 201354
* InstCombine: Replace custom constant folding code with ConstantExpr.Benjamin Kramer2014-02-131-26/+11
| | | | llvm-svn: 201352
* [PR18809] Revert r201187, "DebugInfo: Don't include the name of the CU file ↵NAKAMURA Takumi2014-02-131-0/+3
| | | | | | | | in the line table file list when it's unneeded" It really crashes cygwin's stage2 configure with "clang -g". llvm-svn: 201351
* Use mkdir instead of stat+mkdir.Rafael Espindola2014-02-131-11/+18
| | | | | | | | | | | | | This is an optimistic version of create_diretories: it tries to create the directory first and looks at the parent only if that fails. Running strace on "mkdir -p" shows that it is pessimistic, calling mkdir on every element of the path. We could implement that if needed. In any case, with both strategies there is no reason to call stat, just check the return of mkdir. llvm-svn: 201347
* Reduce code duplication resulting from the ConstantVector/ConstantDataVector ↵Benjamin Kramer2014-02-133-32/+11
| | | | | | | | split. No intended functionality change. llvm-svn: 201344
* Re-commit: Demote EmitRawText call in AsmPrinter::EmitInlineAsm() and remove ↵Daniel Sanders2014-02-1312-7/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | hasRawTextSupport() call Summary: AsmPrinter::EmitInlineAsm() will no longer use the EmitRawText() call for targets with mature MC support. Such targets will always parse the inline assembly (even when emitting assembly). Targets without mature MC support continue to use EmitRawText() for assembly output. The hasRawTextSupport() check in AsmPrinter::EmitInlineAsm() has been replaced with MCAsmInfo::UseIntegratedAs which when true, causes the integrated assembler to parse inline assembly (even when emitting assembly output). UseIntegratedAs is set to true for targets that consider any failure to parse valid assembly to be a bug. Target specific subclasses generally enable the integrated assembler in their constructor. The default value can be overridden with -no-integrated-as. All tests that rely on inline assembly supporting invalid assembly (for example, those that use mnemonics such as 'foo' or 'hello world') have been updated to disable the integrated assembler. Changes since review (and last commit attempt): - Fixed test failures that were missed due to configuration of local build. (fixes crash.ll and a couple others). - Fixed tests that happened to pass because the local build was on X86 (should fix 2007-12-17-InvokeAsm.ll) - mature-mc-support.ll's should no longer require all targets to be compiled. (should fix ARM and PPC buildbots) - Object output (-filetype=obj and similar) now forces the integrated assembler to be enabled regardless of default setting or -no-integrated-as. (should fix SystemZ buildbots) Reviewers: rafael Reviewed By: rafael CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2686 llvm-svn: 201333
* Remove dead code.Rafael Espindola2014-02-132-45/+0
| | | | llvm-svn: 201327
* ARM: remove floating-point patterns for @llvm.arm.neon.vabsTim Northover2014-02-131-3/+0
| | | | | | | The front-end is now generating the generic @llvm.fabs for this operation now, so the extra patterns are no longer needed. llvm-svn: 201314
* Add Cortex-A53 and Cortex-A57 cores to the AArch64 backendOliver Stannard2014-02-131-0/+11
| | | | llvm-svn: 201305
* [AArch64]Fix the problems that can't select mul/add/sub of v1i8/v1i16/v1i32 ↵Hao Liu2014-02-131-4/+160
| | | | | | | | types. As this problems are similar to shl/sra/srl, also add patterns for shift nodes. llvm-svn: 201298
* [RegAlloc] Fix the assertion in the last chance recoloring to match theQuentin Colombet2014-02-131-1/+1
| | | | | | condition at the call site. llvm-svn: 201296
* Copy dll storage in copyAttributes.Rafael Espindola2014-02-131-0/+1
| | | | llvm-svn: 201295
* [DAG] Fix the recognition of opaque constants in the SelectionDAGBuilder.Juergen Ributzka2014-02-131-3/+7
| | | | | | | | | | | This fix checks the original LLVM IR node to identify opaque constants by looking for the bitcast-constant pattern. Originally we looked at the generated SDNode, but this might lead to incorrect results. The SDNode could have been generated by an constant expression that was folded to a constant. This fixes <rdar://problem/16050719> llvm-svn: 201291
* Use simpler version of sys::fs::exists when possible.Rafael Espindola2014-02-131-5/+3
| | | | llvm-svn: 201289
* [AArch64]Add support for spilling FPR8/FPR16.Hao Liu2014-02-131-0/+8
| | | | llvm-svn: 201287
* GlobalOpt: Aliases don't have sections, don't copy them when replacingReid Kleckner2014-02-131-1/+2
| | | | | | | | | | | | | | | | | | | | | As defined in LangRef, aliases do not have sections. However, LLVM's GlobalAlias class inherits from GlobalValue, which means we can read and set its section. We should probably ban that as a separate change, since it doesn't make much sense for an alias to have a section that differs from its aliasee. Fixes PR18757, where the section was being lost on the global in code from Clang like: extern "C" { __attribute__((used, section("CUSTOM"))) static int in_custom_section; } Reviewers: rafael.espindola Differential Revision: http://llvm-reviews.chandlerc.com/D2758 llvm-svn: 201286
* Remove a very old instcombine where we would turn sequences of selects intoOwen Anderson2014-02-121-25/+0
| | | | | | | | | | | | | logical operations on the i1's driving them. This is a bad idea for every target I can think of (confirmed with micro tests on all of: x86-64, ARM, AArch64, Mips, and PowerPC) because it forces the i1 to be materialized into a general purpose register, whereas consuming it directly into a select generally allows it to exist only transiently in a predicate or flags register. Chandler ran a set of performance tests with this change, and reported no measurable change on x86-64. llvm-svn: 201275
* [Vectorizer] Add a new 'OperandValueKind' in TargetTransformInfo calledAndrea Di Biagio2014-02-125-12/+122
| | | | | | | | | | | | | | | | | | | | | | | | | | | 'OK_NonUniformConstValue' to identify operands which are constants but not constant splats. The cost model now allows returning 'OK_NonUniformConstValue' for non splat operands that are instances of ConstantVector or ConstantDataVector. With this change, targets are now able to compute different costs for instructions with non-uniform constant operands. For example, On X86 the cost of a vector shift may vary depending on whether the second operand is a uniform or non-uniform constant. This patch applies the following changes: - The cost model computation now takes into account non-uniform constants; - The cost of vector shift instructions has been improved in X86TargetTransformInfo analysis pass; - BBVectorize, SLPVectorizer and LoopVectorize now know how to distinguish between non-uniform and uniform constant operands. Added a new test to verify that the output of opt '-cost-model -analyze' is valid in the following configurations: SSE2, SSE4.1, AVX, AVX2. llvm-svn: 201272
* [X86] Teach the backend how to lower vector shift left into multiply rather ↵Andrea Di Biagio2014-02-121-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | than scalarizing it. Instead of expanding a packed shift into a sequence of scalar shifts, the backend now tries (when possible) to convert the vector shift into a vector multiply. Before this change, a shift of a MVT::v8i16 vector by a build_vector of constants was always scalarized into a long sequence of "vector extracts + scalar shifts + vector insert". With this change, if there is SSE2 support, we emit a single vector multiply. This change also affects SSE4.1, AVX, AVX2 shifts: - A shift of a MVT::v4i32 vector by a build_vector of non uniform constants is now lowered when possible into a single SSE4.1 vector multiply. - Packed v16i16 shift left by constant build_vector are now expanded when possible into a single AVX2 vpmullw. This change also improves the lowering of AVX512f vector shifts. Added test CodeGen/X86/vec_shift6.ll with some code examples that are affected by this change. llvm-svn: 201271
* Reformat a few lines with clang-format.Eric Christopher2014-02-121-4/+8
| | | | llvm-svn: 201265
* 80-col.Eric Christopher2014-02-121-1/+2
| | | | llvm-svn: 201264
* [Stackmaps] Improve the stackmap lowering code in the SelectionDAGBuilder.Juergen Ributzka2014-02-121-33/+33
| | | | | | | | | | We are now no longer relying on the target-specific call lowering implementation to lower a stackmap intrinsic call. Instead we perform the call lowering in a target-independent way directly in the stackmap lowering code. This simplifies the code and removes the need to fixup the code after the target-specific call lowering. llvm-svn: 201263
* [Stackmaps] Fix the ID type to be i64 also for stackmaps (as we claim in the ↵Juergen Ributzka2014-02-121-6/+7
| | | | | | | | | | | documenation) The ID type for the stackmap and patchpoint intrinsics are in both cases i64. This fixes an zero extend in the SelectionDAGBuilder that still used i32. This also updates the target independent instructions STACKMAP and PATCHPOINT to use the correct type. llvm-svn: 201262
* Extend RTDyld API to enable optionally precomputing the total amount of memoryLang Hames2014-02-123-65/+205
| | | | | | | | | | | | | | | | | | required for all sections in a module. This can be useful when targets or code-models place strict requirements on how sections must be laid out in memory. If RTDyldMemoryManger::needsToReserveAllocationSpace() is overridden to return true then the JIT will call the following method on the memory manager, which can be used to preallocate the necessary memory. void RTDyldMemoryManager::reserveAllocationSpace(uintptr_t CodeSize, uintptr_t DataSizeRO, uintptr_t DataSizeRW) Patch by Vaidas Gasiunas. Thanks very much Viadas! llvm-svn: 201259
* Rename Windows.h to WindowsSupport.h to avoid ambiguityReid Kleckner2014-02-1214-15/+18
| | | | llvm-svn: 201258
* _CS_DARWIN_USER macros available on darwin>=9. Thanks, Dave Odell!David Fang2014-02-121-1/+2
| | | | llvm-svn: 201255
* Debug info: Bugfix for r201190: DW_OP_piece takes bytes, not bits.Adrian Prantl2014-02-122-3/+5
| | | | | | rdar://problem/16015314 llvm-svn: 201253
* Pass edges weights to MachineBasicBlock::addSuccessor in TailDuplicatePass toAkira Hatanaka2014-02-121-2/+14
| | | | | | | | preserve branch probability information. <rdar://problem/15893208> llvm-svn: 201245
* Revert r201237+r201238: Demote EmitRawText call in ↵Daniel Sanders2014-02-1212-64/+7
| | | | | | | | AsmPrinter::EmitInlineAsm() and remove hasRawTextSupport() call It introduced multiple test failures in the buildbots. llvm-svn: 201241
OpenPOWER on IntegriCloud