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* Use llvm.global_ctors to locate global constructors insteadDan Gohman2012-01-181-6/+19
| | | | | | of recognizing them by name. llvm-svn: 148416
* Remove trailing spaces and unneeded includes.Jakub Staszak2012-01-181-134/+131
| | | | llvm-svn: 148415
* Fixed macro condition.Lang Hames2012-01-181-1/+1
| | | | llvm-svn: 148408
* Tidy up. 80 columns.Jim Grosbach2012-01-181-13/+13
| | | | llvm-svn: 148401
* Tidy up. MCAsmBackend naming conventions.Jim Grosbach2012-01-188-48/+48
| | | | llvm-svn: 148400
* Remove dead code.Bill Wendling2012-01-181-45/+0
| | | | llvm-svn: 148384
* Fix a bug in the type-legalization of vector integers. When we bitcast one ↵Nadav Rotem2012-01-181-2/+4
| | | | | | vector type to another, we must not bitcast the result if one type is widened while the other is promoted. llvm-svn: 148383
* Fix ISD::REG_SEQUENCE to accept physical registers and change ↵Pete Cooper2012-01-182-16/+24
| | | | | | TwoAddressInstructionPass to insert copies for any physical reg operands of the REG_SEQUENCE llvm-svn: 148377
* Thumb2 load/store fixups don't set the thumb bit.Jim Grosbach2012-01-181-4/+8
| | | | | | | | | | Load/store instructions w/ a fixup to be relative a function marked as thumb don't use the low bit to specify thumb vs. non-thumb like interworking branches do, so don't set it when dealing with those fixups. rdar://10348687. llvm-svn: 148366
* Move some ARM specific MCAssmebler bits into the ARMAsmBackend.Jim Grosbach2012-01-182-9/+17
| | | | llvm-svn: 148364
* Add a CoveredBySubRegs property to Register descriptions.Jakob Stoklund Olesen2012-01-185-2/+6
| | | | | | | | | | | | | | | | When set, this bit indicates that a register is completely defined by the value of its sub-registers. Use the CoveredBySubRegs property to infer which super-registers are call-preserved given a list of callee-saved registers. For example, the ARM registers D8-D15 are callee-saved. This now automatically implies that Q4-Q7 are call-preserved. Conversely, Win64 callees save XMM6-XMM15, but the corresponding YMM6-YMM15 registers are not call-preserved because they are not fully defined by their sub-registers. llvm-svn: 148363
* Implement ARMBaseRegisterInfo::getCallPreservedMask().Jakob Stoklund Olesen2012-01-173-19/+17
| | | | | | Move ARM callee-saved lists into ARMCallingConv.td. llvm-svn: 148357
* Fix MCJIT memory leak of owned TargetMachine.Jim Grosbach2012-01-171-0/+1
| | | | | | | The JIT is expected to take ownership of the TM that's passed in. The MCJIT wasn't freeing it, resulting in leaks. llvm-svn: 148356
* Move X86 callee saved register lists to the X86CallConv .td file.Jakob Stoklund Olesen2012-01-173-37/+37
| | | | | | Add a trivial implementation of the getCallPreservedMask() hook. llvm-svn: 148347
* Move includes to the .cpp file.Jakub Staszak2012-01-171-0/+2
| | | | llvm-svn: 148342
* MC tweak symbol difference resolution for non-local symbols.Jim Grosbach2012-01-171-2/+2
| | | | | | | | | | | | | | When the non-local symbol in the expression is in the same fragment as the second symbol, the assembler can still evaluate the expression without needing a relocation. For example, on ARM: _foo: ldr lr, (_foo - 4) rdar://10348687 llvm-svn: 148341
* Intel syntax: Fix parser match class to check memory operand size.Devang Patel2012-01-171-3/+3
| | | | llvm-svn: 148338
* Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.Nadav Rotem2012-01-171-4/+35
| | | | llvm-svn: 148337
* Intel syntax: Parse "BYTE PTR [RDX + RCX]"Devang Patel2012-01-171-0/+4
| | | | llvm-svn: 148334
* Add a new ObjC ARC optimization pass to eliminate unneededDan Gohman2012-01-172-1/+118
| | | | | | autorelease push+pop pairs. llvm-svn: 148330
* Add a new PassManagerBuilder customization point,Dan Gohman2012-01-171-0/+2
| | | | | | | EP_ModuleOptimizerEarly, to allow passes to be added before the main ModulePass optimizers. llvm-svn: 148329
* Untabify.Devang Patel2012-01-171-12/+12
| | | | llvm-svn: 148322
* Intel syntax: Do not unncessarily create plus expression for memory operand ↵Devang Patel2012-01-171-2/+1
| | | | | | displacement. llvm-svn: 148321
* Intel syntax: Robustify memory operand parsing.Devang Patel2012-01-171-51/+113
| | | | llvm-svn: 148312
* Removes template magic to build up containers.Manuel Klimek2012-01-171-7/+82
| | | | | | Instead, we now put the attributes of the container into members. llvm-svn: 148302
* Fix warning.Nadav Rotem2012-01-171-1/+1
| | | | llvm-svn: 148301
* Fix 11769.Nadav Rotem2012-01-171-0/+7
| | | | | | | | In CanXFormVExtractWithShuffleIntoLoad we assumed that EXTRACT_VECTOR_ELT can be later handled by the DAGCombiner. However, in some cases on AVX, the EXTRACT_VECTOR_ELT is legalized to EXTRACT_SUBVECTOR + EXTRACT_VECTOR_ELT, which currently is not handled by the DAGCombiner. In this patch I added a check that we only extract from the XMM part. llvm-svn: 148298
* Teach DAG combiner to turn a BUILD_VECTOR of UNDEFs into an UNDEF of vector ↵Craig Topper2012-01-171-4/+8
| | | | | | type. llvm-svn: 148297
* Remove unnecessary AVX check from an assert. hasSSE2 is enough.Craig Topper2012-01-171-2/+1
| | | | llvm-svn: 148295
* Provide better messages in llvm_unreachable.David Blaikie2012-01-171-1/+1
| | | | llvm-svn: 148293
* misched: Inital interface and implementation for ScheduleTopDownLive and ↵Andrew Trick2012-01-171-17/+130
| | | | | | ShuffleInstructions. llvm-svn: 148291
* Renamed MachineScheduler to ScheduleTopDownLive.Andrew Trick2012-01-174-51/+63
| | | | | | Responding to code review. llvm-svn: 148290
* Moving options declarations around.Andrew Trick2012-01-173-10/+7
| | | | | | More short term hackery until we have a way to configure passes that work on LiveIntervals. llvm-svn: 148289
* LSR fix: broaden the check for loop preheaders.Andrew Trick2012-01-171-5/+13
| | | | | | | It's becoming clear that LoopSimplify needs to unconditionally create loop preheaders. But that is a bigger fix. For now, continuing to hack LSR. Fixes rdar://10701050 "Cannot split an edge from an IndirectBrInst" assert. llvm-svn: 148288
* Fix a crasher when PerformShiftCombine receives a BUILD_VECTOR of all UNDEF. ↵Craig Topper2012-01-171-0/+5
| | | | | | Probably could use better handling in DAG combine or getNode. Fixes PR11772. llvm-svn: 148285
* Remove unreachable code. (replace with llvm_unreachable to help GCC where ↵David Blaikie2012-01-177-9/+9
| | | | | | necessary) llvm-svn: 148284
* Add 148175 back. I am unable to reproduce any non determinism in a dragoneggRafael Espindola2012-01-171-2/+4
| | | | | | | | | | | or clang bootstrap. I will keep an eye on the bots. Original message: Only emit the Leh_func_endN symbol when needed. llvm-svn: 148283
* Changed flag operand of ISD::FP_ROUND to TargetConstant as it should not get ↵Pete Cooper2012-01-171-2/+3
| | | | | | checked for legalisation llvm-svn: 148275
* Fix typo in comment.Lang Hames2012-01-171-1/+1
| | | | llvm-svn: 148268
* Tidy up.Jim Grosbach2012-01-164-5/+5
| | | | llvm-svn: 148265
* ExecutionEngine interface to re-map addresses for engines that support it.Jim Grosbach2012-01-164-1/+31
| | | | llvm-svn: 148264
* MCJIT handle a few more simple x86 relocations for MachO.Jim Grosbach2012-01-161-4/+5
| | | | llvm-svn: 148263
* Removing unused default switch cases in switches over enums that already ↵David Blaikie2012-01-168-23/+3
| | | | | | | | account for all enumeration values explicitly. (This time I believe I've checked all the -Wreturn-type warnings from GCC & added the couple of llvm_unreachables necessary to silence them. If I've missed any, I'll happily fix them as soon as I know about them) llvm-svn: 148262
* Cleanup PPC RLWINM8 vs RLWINMHal Finkel2012-01-161-1/+1
| | | | | | No test case: output assembly will be identical. llvm-svn: 148261
* AggressiveAntiDepBreaker needs to skip debug values because a debug value ↵Hal Finkel2012-01-161-0/+3
| | | | | | does not have a corresponding SUnit llvm-svn: 148260
* Extract method for detecting constant unallocatable physregs.Jakob Stoklund Olesen2012-01-164-41/+21
| | | | | | It is safe to move uses of such registers. llvm-svn: 148259
* MCJIT support for non-function sections.Jim Grosbach2012-01-166-266/+447
| | | | | | | | | | | | | | | | Move to a by-section allocation and relocation scheme. This allows better support for sections which do not contain externally visible symbols. Flesh out the relocation address vs. local storage address separation a bit more as well. Remote process JITs use this to tell the relocation resolution code where the code will live when it executes. The startFunctionBody/endFunctionBody interfaces to the JIT and the memory manager are deprecated. They'll stick around for as long as the old JIT does, but the MCJIT doesn't use them anymore. llvm-svn: 148258
* Fixed comment in loop-unswitch.Stepan Dyatkovskiy2012-01-161-1/+1
| | | | llvm-svn: 148252
* Give better scavenger errors by invoking the verifier.Jakob Stoklund Olesen2012-01-161-1/+6
| | | | llvm-svn: 148251
* Add a new kind of MachineOperand: MO_RegisterMask.Jakob Stoklund Olesen2012-01-161-0/+5
| | | | | | | | | | | | | | | | | | | | | Register masks will be used as a compact representation of large clobber lists. Currently, an x86 call instruction has some 40 operands representing call-clobbered registers. That's more than 1kB of useless operands per call site. A register mask operand references a bit mask of call-preserved registers, everything else is clobbered. The bit mask will typically come from TargetRegisterInfo::getCallPreservedMask(). By abandoning ImplicitDefs for call-clobbered registers, it also becomes possible to share call instruction descriptions between calling conventions, and we can get rid of the WINCALL* instructions. This patch introduces the new operand kind. Future patches will add RegMask support to target-independent passes before finally the fixed clobber lists can be removed from call instruction descriptions. llvm-svn: 148250
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