summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* [AArch64][SVE2] Asm: add SADALP and UADALP instructionsCullen Rhodes2019-05-202-0/+31
| | | | | | | | | | | | | | | Summary: This patch adds support for the integer pairwise add and accumulate long instructions SADALP/UADALP. These instructions are predicated. The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D62001 llvm-svn: 361154
* [InstSimplify] Teach fsub -0.0, (fneg X) ==> X about unary fnegCameron McInally2019-05-201-1/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D62077 llvm-svn: 361151
* Resubmit "[DebugInfo] Update loop metadata for inlined loops"Orlando Cazalet-Hyams2019-05-201-3/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 95805bc425b264805a472232a75ed2ffe58aceda. I've squashed the test fix into this commit. [DebugInfo] Update loop metadata for inlined loops Currently, when a loop is cloned while inlining function (A) into function (B) the loop metadata is copied and then not modified at all. The loop metadata can encode the loop's start and end DILocations. Therefore, the new inlined loop in function (B) may have loop metadata which shows start and end locations residing in function (A). This patch ensures loop metadata is updated while inlining so that the start and end DILocations are given the "inlinedAt" operand. I've also added a regression test for this. This fix is required for D60831 because that patch uses loop metadata to determine the DILocation for the branches of new loop preheaders. Reviewers: aprantl, dblaikie, anemet Reviewed By: aprantl Subscribers: eraman, hiraditya, llvm-commits Tags: #debug-info, #llvm Differential Revision: https://reviews.llvm.org/D61933 llvm-svn: 361149
* Revert "[DebugInfo] Update loop metadata for inlined loops"Orlando Cazalet-Hyams2019-05-201-48/+3
| | | | | | | This reverts commit 6e8f1a80cd988db8870aff9c3bc2ca7a20e04104. Reverting patch while investigating build bot failure. llvm-svn: 361143
* [NFC] Refactor visitIntrinsicCall so it doesn't return a const char*Guillaume Chatelet2019-05-202-141/+148
| | | | | | | | | | | | | | Summary: API simplification Reviewers: courbet Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D61306 llvm-svn: 361140
* [DebugInfoMetadata] Refactor DIExpression::prepend constants (NFC)Petar Jovanovic2019-05-2014-41/+40
| | | | | | | | | | | Refactor DIExpression::With* into a flag enum in order to be less error-prone to use (as discussed on D60866). Patch by Djordje Todorovic. Differential Revision: https://reviews.llvm.org/D61943 llvm-svn: 361137
* [AArch64][SVE2] Asm: add int halving add/sub (predicated) instructionsCullen Rhodes2019-05-202-0/+43
| | | | | | | | | | | | | | | | | | Summary: This patch adds support for the predicated integer halving add/sub instructions: * SHADD, UHADD, SRHADD, URHADD * SHSUB, UHSUB, SHSUBR, UHSUBR The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: rovka Differential Revision: https://reviews.llvm.org/D62000 llvm-svn: 361136
* [AArch64][SVE2] Asm: add saturating multiply-add interleaved long instructionsCullen Rhodes2019-05-201-0/+4
| | | | | | | | | | | | | | Summary: Patch adds support for SQDMLALBT and SQDMLSLBT instructions. The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: rovka Differential Revision: https://reviews.llvm.org/D61998 llvm-svn: 361135
* Use llvm::sort. NFCFangrui Song2019-05-204-14/+10
| | | | llvm-svn: 361134
* Match types of accumulator and result for ↵Sander de Smalen2019-05-201-4/+2
| | | | | | | | | | | | | | | | | llvm.experimental.vector.reduce.fadd/fmul The scalar start/accumulator value of the fadd- and fmul reduction should match the result type of the reduction, as well as the vector element-type of the input vector. Although this was not explicitly specified in the LangRef, it was taken for granted in code implementing the reductions. The patch also fixes the LangRef by adding this constraint. Reviewed By: aemerson, nikic Differential Revision: https://reviews.llvm.org/D60260 llvm-svn: 361133
* [DebugInfo] Update loop metadata for inlined loopsOrlando Cazalet-Hyams2019-05-201-3/+48
| | | | | | | | | | | | | | | | | | | | | Summary: Currently, when a loop is cloned while inlining function (A) into function (B) the loop metadata is copied and then not modified at all. The loop metadata can encode the loop's start and end DILocations. Therefore, the new inlined loop in function (B) may have loop metadata which shows start and end locations residing in function (A). This patch ensures loop metadata is updated while inlining so that the start and end DILocations are given the "inlinedAt" operand. I've also added a regression test for this. This fix is required for D60831 because that patch uses loop metadata to determine the DILocation for the branches of new loop preheaders. Reviewers: aprantl, dblaikie, anemet Reviewed By: aprantl Subscribers: eraman, hiraditya, llvm-commits Tags: #debug-info, #llvm Differential Revision: https://reviews.llvm.org/D61933 llvm-svn: 361132
* Revert "[NFC] Refactor visitIntrinsicCall so it doesn't return a const char*"Guillaume Chatelet2019-05-202-145/+138
| | | | | | This reverts commit 706d3cd6388cc3446aab282f3af879862b10cbed. llvm-svn: 361130
* [NFC] Refactor visitIntrinsicCall so it doesn't return a const char*Guillaume Chatelet2019-05-202-138/+145
| | | | | | | | | | | | | | Summary: API simplification Reviewers: courbet Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D61306 llvm-svn: 361129
* [AMDGPU] gfx1010 Avoid SMEM WAR hazard for some s_waitcnt valuesCarl Ritson2019-05-201-6/+22
| | | | | | | | | | | | | | | | | | Summary: Avoid introducing hazard mitigation when lgkmcnt is reduced to 0. Clarify code comments to explain assumptions made for this hazard mitigation. Expand and correct test cases to cover variants of s_waitcnt. Reviewers: nhaehnle, rampitec Subscribers: arsenm, kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62058 llvm-svn: 361124
* [InstSimplify] fold fcmp (maxnum, X, C1), C2Sanjay Patel2019-05-191-16/+26
| | | | | | | | | | | | | This is the sibling transform for rL360899 (D61691): maxnum(X, GreaterC) == C --> false maxnum(X, GreaterC) <= C --> false maxnum(X, GreaterC) < C --> false maxnum(X, GreaterC) >= C --> true maxnum(X, GreaterC) > C --> true maxnum(X, GreaterC) != C --> true llvm-svn: 361118
* [SLP] Refactoring of EdgeInfo and UserTreeIdx in buildTree_rec().Dinar Temirbulatov2019-05-191-58/+48
| | | | | | | | | | | This is a follow-up refactoring patch after the introduction of usable TreeEntry pointers in D61706. The EdgeInfo struct can now use a TreeEntry pointer instead of an index in VectorizableTree. Committed on behalf of @vporpo (Vasileios Porpodas) Differential Revision: https://reviews.llvm.org/D61795 llvm-svn: 361110
* [X86] Remove combineShift function. Just dispatch directly to the handler ↵Craig Topper2019-05-191-21/+3
| | | | | | for each flavor from the main switch. NFC llvm-svn: 361108
* GVN: Handle addrspacecastMatt Arsenault2019-05-181-0/+1
| | | | llvm-svn: 361103
* MemCmpExpansion::getCompareLoadPairs - assert we find a comparison diff. NFCI.Simon Pilgrim2019-05-181-1/+3
| | | | | | Fix scan-build uninitialized warning and assert the final diff isn't null. llvm-svn: 361095
* AMDGPU/GlobalISel: Implement s64->s64 [SU]ITOFPMatt Arsenault2019-05-172-0/+39
| | | | llvm-svn: 361082
* GlobalISel: Implement lower for S64->S32 [SU]ITOFPMatt Arsenault2019-05-172-0/+122
| | | | | | | | | | | | | This is ported from the custom AMDGPU DAG implementation. I think this is a better default expansion than what the DAG currently uses, at least if the target has CTLZ. This implements the signed version in terms of the unsigned conversion, which is implemented with bit operations. SelectionDAG has several other implementations that should eventually be ported depending on what instructions are legal. llvm-svn: 361081
* [WebAssembly] Remove expected failure of builtin-location.C testSam Clegg2019-05-171-1/+0
| | | | | | | | | | This seems to have been fixed by https://reviews.llvm.org/D61956 Yay Differential Revision: https://reviews.llvm.org/D62075 llvm-svn: 361071
* GlobalISel: Define integer min/max instructionsMatt Arsenault2019-05-171-1/+5
| | | | | | | Doesn't attempt to emit them for anything yet, but some legalizations I want to port use them. llvm-svn: 361061
* [InstCombine] move bitcast after insertelement-with-bitcasted-operandsSanjay Patel2019-05-171-0/+14
| | | | llvm-svn: 361058
* [X86][SSE] Fold movmsk(not(x)) -> not(movmsk)Simon Pilgrim2019-05-171-1/+14
| | | | | | Helps to improve folding of comparisons with movmsk results. llvm-svn: 361056
* [X86][SSE] Match all-of bool scalar reductions into a bitcast/movmsk + cmp.Simon Pilgrim2019-05-171-0/+18
| | | | | | Same as what we do for vector reductions in combineHorizontalPredicateResult, use movmsk+cmp for scalar (and(extract(x,0),extract(x,1)) reduction patterns. llvm-svn: 361052
* [InstSimplify] Add unary fneg to `fsub 0.0, (fneg X) ==> X` transformCameron McInally2019-05-171-1/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D62013 llvm-svn: 361047
* [AMDGPU][MC] Corrected parsing of NAME:VALUE modifiersDmitry Preobrazhensky2019-05-171-33/+17
| | | | | | | | | | See bug 41298: https://bugs.llvm.org/show_bug.cgi?id=41298 Reviewers: artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D61009 llvm-svn: 361045
* [DAGCombiner] visitShiftByConstant(): drop bogus signbit checkRoman Lebedev2019-05-171-18/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: That check claims that the transform is illegal otherwise. That isn't true: 1. For `ISD::ADD`, we only process `ISD::SHL` outer shift => sign bit does not matter https://rise4fun.com/Alive/K4A 2. For `ISD::AND`, there is no restriction on constants: https://rise4fun.com/Alive/Wy3 3. For `ISD::OR`, there is no restriction on constants: https://rise4fun.com/Alive/GOH 3. For `ISD::XOR`, there is no restriction on constants: https://rise4fun.com/Alive/ml6 So, why is it there then? This changes the testcase that was touched by @spatel in rL347478, but i'm not sure that test tests anything particular? Reviewers: RKSimon, spatel, craig.topper, jojo, rengolin Reviewed By: spatel Subscribers: javed.absar, llvm-commits, spatel Tags: #llvm Differential Revision: https://reviews.llvm.org/D61918 llvm-svn: 361044
* [InstCombine] canShiftBinOpWithConstantRHS(): drop bogus signbit checkRoman Lebedev2019-05-171-26/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: In D61918 i was looking at dropping it in DAGCombiner `visitShiftByConstant()`, but as @craig.topper pointed out, it was copied from here. That check claims that the transform is illegal otherwise. That isn't true: 1. For `ISD::ADD`, we only process `ISD::SHL` outer shift => sign bit does not matter https://rise4fun.com/Alive/K4A 2. For `ISD::AND`, there is no restriction on constants: https://rise4fun.com/Alive/Wy3 3. For `ISD::OR`, there is no restriction on constants: https://rise4fun.com/Alive/GOH 3. For `ISD::XOR`, there is no restriction on constants: https://rise4fun.com/Alive/ml6 So, why is it there then? As far as i can tell, it dates all the way back to original check-in rL7793. I think we should just drop it. Reviewers: spatel, craig.topper, efriedma, majnemer Reviewed By: spatel Subscribers: llvm-commits, craig.topper Tags: #llvm Differential Revision: https://reviews.llvm.org/D61938 llvm-svn: 361043
* [AMDGPU][MC] Enabled labels with s_call_b64 and s_cbranch_i_forkDmitry Preobrazhensky2019-05-171-2/+2
| | | | | | | | | | See https://bugs.llvm.org/show_bug.cgi?id=41888 Reviewers: artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D62016 llvm-svn: 361040
* [X86][AVX] Remove LowerCTTZ's AVX1 custom vector handling.Simon Pilgrim2019-05-171-7/+0
| | | | | | We can now rely on generic expansion to handle this. llvm-svn: 361038
* [X86][AVX] isNOT - add extract_subvector(xor X, -1) -> extract_subvector(X) ↵Simon Pilgrim2019-05-171-0/+9
| | | | | | | | fold. Prep work for the removal of the remaining x86 CTTZ vector lowering. llvm-svn: 361035
* [AMDGPU][MC] Enabled expressions for most operands which accept integer valuesDmitry Preobrazhensky2019-05-172-65/+110
| | | | | | | | | | See bug 40873: https://bugs.llvm.org/show_bug.cgi?id=40873 Reviewers: artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D60768 llvm-svn: 361031
* AMDGPU: Fix unused variable warnings in release buildsMatt Arsenault2019-05-171-12/+9
| | | | llvm-svn: 361030
* AMDGPU/GlobalISel: Legalize G_FCEILMatt Arsenault2019-05-172-2/+37
| | | | llvm-svn: 361028
* AMDGPU/GlobalISel: Legalize G_INTRINSIC_TRUNCMatt Arsenault2019-05-172-4/+70
| | | | llvm-svn: 361027
* AMDGPU/GlobalISel: Legalize G_FRINTMatt Arsenault2019-05-172-0/+44
| | | | llvm-svn: 361026
* AMDGPU/GlobalISel: Legalize G_FCOPYSIGNMatt Arsenault2019-05-172-0/+5
| | | | llvm-svn: 361025
* [MergeICmps][NFC] Add more debug.Clement Courbet2019-05-171-0/+9
| | | | llvm-svn: 361024
* AMDGPU/GlobalISel: RegBankSelect for llvm.amdgcn.s.buffer.loadMatt Arsenault2019-05-171-0/+44
| | | | llvm-svn: 361023
* AMDGPU/GlobalISel: Use subreg index instead of extra unmergeMatt Arsenault2019-05-171-8/+2
| | | | | | | This saves instructions and extra steps, but I'm not sure about introducing subregister indexes at this point. llvm-svn: 361022
* AMDGPU/GlobalISel: Use waterfall loop for buffer_loadMatt Arsenault2019-05-172-36/+302
| | | | | | | This adds support for more complex waterfall loops that need to handle operands > 32-bits, and multiple operands. llvm-svn: 361021
* [X86] Pull out IsNOT helper. NFCI.Simon Pilgrim2019-05-171-8/+16
| | | | | | Return the input value for the NOT pattern: (xor X, -1) -> X llvm-svn: 361012
* Re-land r360859: "[MergeICmps] Simplify the code."Clement Courbet2019-05-171-145/+151
| | | | | | | | | | With a fix for PR41917: The predecessor list was changing under our feet. - for (BasicBlock *Pred : predecessors(EntryBlock_)) { + while (!pred_empty(EntryBlock_)) { + BasicBlock* const Pred = *pred_begin(EntryBlock_); llvm-svn: 361009
* [AMDGPU] detect WaW hazards when moving/merging load/store instructionsRhys Perry2019-05-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: In order to combine memory operations efficiently, the load/store optimizer might move some instructions around. It's usually safe to move instructions down past the merged instruction because the pass checks if memory operations can be re-ordered. Though, the current logic doesn't handle Write-after-Write hazards. This fixes a reflection issue with Monster Hunter World and DXVK. v2: - rebased on top of master - clean up the test case - handle WaW hazards correctly Bugzilla: https://bugs.llvm.org/show_bug.cgi?id=40130 Original patch by Samuel Pitoiset. Reviewers: tpr, arsenm, nhaehnle Reviewed By: nhaehnle Subscribers: ronlieb, arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye Differential Revision: https://reviews.llvm.org/D61313 llvm-svn: 361008
* [AArch64][SVE2] Asm: add saturating multiply-add long instructionsCullen Rhodes2019-05-171-0/+12
| | | | | | | | | | | | | | | | | Summary: Patch adds support for indexed and unpredicated vectors forms of the following instructions: * SQDMLALB, SQDMLALT, SQDMLSLB, SQDMLSLT The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D61997 llvm-svn: 361005
* [AArch64][SVE2] Asm: add integer multiply-add long instructionsCullen Rhodes2019-05-172-0/+49
| | | | | | | | | | | | | | | | | Summary: Patch adds support for indexed and unpredicated vectors forms of the following instructions: * SMLALB, SMLALT, UMLALB, UMLALT, SMLSLB, SMLSLT, UMLSLB, UMLSLT The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: rovka Differential Revision: https://reviews.llvm.org/D61951 llvm-svn: 361003
* [AArch64][SVE2] Asm: add integer multiply long instructionsCullen Rhodes2019-05-172-0/+64
| | | | | | | | | | | | | | | | | Summary: Patch adds support for indexed and unpredicated vectors forms of the following instructions: * SMULLB, SMULLT, UMULLB, UMULLT, SQDMULLB, SQDMULLT The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: rovka Differential Revision: https://reviews.llvm.org/D61936 llvm-svn: 361002
* [X86] Add FeatureFastScalarShiftMasks and FeatureFastVectorShiftMasks to the ↵Craig Topper2019-05-171-0/+2
| | | | | | | | | ignore list for inlining compatibility. These are tuning flags and won't cause any codegen issue if we inline a function with a different value. llvm-svn: 360992
OpenPOWER on IntegriCloud