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| author | Cullen Rhodes <cullen.rhodes@arm.com> | 2019-05-17 09:19:41 +0000 |
|---|---|---|
| committer | Cullen Rhodes <cullen.rhodes@arm.com> | 2019-05-17 09:19:41 +0000 |
| commit | 334130a199c05aa18b1b7ffbafc50c982a5f797b (patch) | |
| tree | 8834adb10c0f4653ada35a7bb862a0642f3519f2 /llvm/lib | |
| parent | 0d47f0082159c70a976d2e6d6aa9994ec171203a (diff) | |
| download | bcm5719-llvm-334130a199c05aa18b1b7ffbafc50c982a5f797b.tar.gz bcm5719-llvm-334130a199c05aa18b1b7ffbafc50c982a5f797b.zip | |
[AArch64][SVE2] Asm: add integer multiply-add long instructions
Summary:
Patch adds support for indexed and unpredicated vectors forms of the
following instructions:
* SMLALB, SMLALT, UMLALB, UMLALT, SMLSLB, SMLSLT, UMLSLB, UMLSLT
The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest
Reviewed By: rovka
Differential Revision: https://reviews.llvm.org/D61951
llvm-svn: 361003
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 20 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/SVEInstrFormats.td | 29 |
2 files changed, 49 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index 5685a75dd23..5535d784289 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -1077,6 +1077,26 @@ let Predicates = [HasSVE2] in { defm SQDMULLB_ZZZI : sve2_int_mul_long_by_indexed_elem<0b100, "sqdmullb">; defm SQDMULLT_ZZZI : sve2_int_mul_long_by_indexed_elem<0b101, "sqdmullt">; + // SVE2 integer multiply-add long (indexed) + defm SMLALB_ZZZI : sve2_int_mla_long_by_indexed_elem<0b1000, "smlalb">; + defm SMLALT_ZZZI : sve2_int_mla_long_by_indexed_elem<0b1001, "smlalt">; + defm UMLALB_ZZZI : sve2_int_mla_long_by_indexed_elem<0b1010, "umlalb">; + defm UMLALT_ZZZI : sve2_int_mla_long_by_indexed_elem<0b1011, "umlalt">; + defm SMLSLB_ZZZI : sve2_int_mla_long_by_indexed_elem<0b1100, "smlslb">; + defm SMLSLT_ZZZI : sve2_int_mla_long_by_indexed_elem<0b1101, "smlslt">; + defm UMLSLB_ZZZI : sve2_int_mla_long_by_indexed_elem<0b1110, "umlslb">; + defm UMLSLT_ZZZI : sve2_int_mla_long_by_indexed_elem<0b1111, "umlslt">; + + // SVE2 integer multiply-add long (vectors, unpredicated) + defm SMLALB_ZZZ : sve2_int_mla_long<0b10000, "smlalb">; + defm SMLALT_ZZZ : sve2_int_mla_long<0b10001, "smlalt">; + defm UMLALB_ZZZ : sve2_int_mla_long<0b10010, "umlalb">; + defm UMLALT_ZZZ : sve2_int_mla_long<0b10011, "umlalt">; + defm SMLSLB_ZZZ : sve2_int_mla_long<0b10100, "smlslb">; + defm SMLSLT_ZZZ : sve2_int_mla_long<0b10101, "smlslt">; + defm UMLSLB_ZZZ : sve2_int_mla_long<0b10110, "umlslb">; + defm UMLSLT_ZZZ : sve2_int_mla_long<0b10111, "umlslt">; + // SVE2 integer multiply long defm SQDMULLB_ZZZ : sve2_wide_int_arith_long<0b11000, "sqdmullb">; defm SQDMULLT_ZZZ : sve2_wide_int_arith_long<0b11001, "sqdmullt">; diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index 8b07ccdba4b..c0d3ff03890 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -1722,6 +1722,12 @@ multiclass sve2_int_mla<bit S, string asm> { def _D : sve2_int_mla<0b11, { 0b1110, S }, asm, ZPR64, ZPR64>; } +multiclass sve2_int_mla_long<bits<5> opc, string asm> { + def _H : sve2_int_mla<0b01, opc, asm, ZPR16, ZPR8>; + def _S : sve2_int_mla<0b10, opc, asm, ZPR32, ZPR16>; + def _D : sve2_int_mla<0b11, opc, asm, ZPR64, ZPR32>; +} + //===----------------------------------------------------------------------===// // SVE2 Integer Multiply-Add - Indexed Group //===----------------------------------------------------------------------===// @@ -1768,6 +1774,29 @@ multiclass sve2_int_mla_by_indexed_elem<bits<2> opc, bit S, string asm> { } //===----------------------------------------------------------------------===// +// SVE2 Integer Multiply-Add Long - Indexed Group +//===----------------------------------------------------------------------===// + +multiclass sve2_int_mla_long_by_indexed_elem<bits<4> opc, string asm> { + def _S : sve2_int_mla_by_indexed_elem<0b10, { opc{3}, 0b0, opc{2-1}, ?, opc{0} }, + asm, ZPR32, ZPR16, ZPR3b16, VectorIndexH> { + bits<3> Zm; + bits<3> iop; + let Inst{20-19} = iop{2-1}; + let Inst{18-16} = Zm; + let Inst{11} = iop{0}; + } + def _D : sve2_int_mla_by_indexed_elem<0b11, { opc{3}, 0b0, opc{2-1}, ?, opc{0} }, + asm, ZPR64, ZPR32, ZPR4b32, VectorIndexS> { + bits<4> Zm; + bits<2> iop; + let Inst{20} = iop{1}; + let Inst{19-16} = Zm; + let Inst{11} = iop{0}; + } +} + +//===----------------------------------------------------------------------===// // SVE Integer Dot Product Group //===----------------------------------------------------------------------===// |

