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* X86: Don't generate 64-bit movd after cmpneqsd in 32-bit mode (PR19059)Hans Wennborg2014-03-111-4/+20
| | | | | | | | | This fixes the bug where we would bitcast the 64-bit floating point result of cmpneqsd to a 64-bit integer even on 32-bit targets. Differential Revision: http://llvm-reviews.chandlerc.com/D3009 llvm-svn: 203581
* [ppc64] Patch in TOC restore code after all external function callsUlrich Weigand2014-03-111-3/+3
| | | | | | | | | | | | | | | | When resolving a function call to an external routine, the dynamic loader must patch the "nop" after the branch instruction to a load that restores the TOC register. Current code does that, but only with the *first* instance of a call to any particular external routine, i.e. at the point where it also allocates the call stub. With subsequent calls to the same routine, current code neglects to patch in the TOC restore code. This is a bug, and leads to corrupt TOC pointers in those cases. Fixed by patching in restore code every time. llvm-svn: 203580
* ARM: honour -f{no-,}optimize-sibling-callsSaleem Abdulrasool2014-03-111-2/+4
| | | | | | | | | | | Use the options in the ARMISelLowering to control whether tail calls are optimised or not. Previously, this option was entirely ignored on the ARM target and only honoured on x86. This option is mostly useful in profiling scenarios. The default remains that tail call optimisations will be applied. llvm-svn: 203577
* ARM: remove ancient -arm-tail-calls optionSaleem Abdulrasool2014-03-111-8/+2
| | | | | | | | This option is from 2010, designed to work around a linker issue on Darwin for ARM. According to grosbach this is no longer an issue and this option can safely be removed. llvm-svn: 203576
* ARM: enable tail call optimisation on Thumb 2Saleem Abdulrasool2014-03-111-1/+3
| | | | | | | | | | | | Tail call optimisation was previously disabled on all targets other than iOS5.0+. This enables the tail call optimisation on all Thumb 2 capable platforms. The test adjustments are to remove the IR hint "tail" to function invocation. The tests were designed assuming that tail call optimisations would not kick in which no longer holds true. llvm-svn: 203575
* Fix crash in PRE.Erik Verbruggen2014-03-111-0/+2
| | | | | | | | | | After r203553 overflow intrinsics and their non-intrinsic (normal) instruction get hashed to the same value. This patch prevents PRE from moving an instruction into a predecessor block, and trying to add a phi node that gets two different types (the intrinsic result and the non-intrinsic result), resulting in a failing assert. llvm-svn: 203574
* ARM: simplify EmitAtomicBinary64Tim Northover2014-03-113-34/+19
| | | | | | | | | ATOMIC_STORE operations always get here as a lowered ATOMIC_SWAP, so there's no need for any code to handle them specially. There should be no functionality change so no tests. llvm-svn: 203567
* Remove copy ctors that did the same thing as the default one.Benjamin Kramer2014-03-112-18/+0
| | | | | | | The code added nothing but potentially disabled move semantics and made types non-trivially copyable. llvm-svn: 203563
* IR: add a second ordering operand to cmpxhg for failureTim Northover2014-03-1120-66/+170
| | | | | | | | | | | | | | | The syntax for "cmpxchg" should now look something like: cmpxchg i32* %addr, i32 42, i32 3 acquire monotonic where the second ordering argument gives the required semantics in the case that no exchange takes place. It should be no stronger than the first ordering constraint and cannot be either "release" or "acq_rel" (since no store will have taken place). rdar://problem/15996804 llvm-svn: 203559
* GVN: fix hashing of extractvalue.Erik Verbruggen2014-03-111-0/+4
| | | | | | | My last commit did not add the indexes to the hashed value for extractvalue. Adding that back in. llvm-svn: 203558
* GVN: merge overflow intrinsics with non-overflow instructions.Erik Verbruggen2014-03-111-58/+118
| | | | | | | | | | | | | | | | | | | When an overflow intrinsic is followed by a non-overflow instruction, replace the latter with an extract. For example: %sadd = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %a, i32 %b) %sadd3 = add i32 %a, %b Here the add statement will be replaced by an extract. When an overflow intrinsic follows a non-overflow instruction, a clone of the intrinsic is inserted before the normal instruction, which makes it the same as the previous case. Subsequent runs of GVN can then clean up the duplicate instructions and insert the extract. This fixes PR8817. llvm-svn: 203553
* Object: rename ARMV7 to ARMNTSaleem Abdulrasool2014-03-111-1/+1
| | | | | | | The official specifications state the name to be ARMNT (as per the Microsoft Portable Executable and Common Object Format Specification v8.3). llvm-svn: 203530
* Cleanup whitespaceDuncan P. N. Exon Smith2014-03-111-9/+9
| | | | llvm-svn: 203529
* R600: Calculate store mask instead of using switch.Matt Arsenault2014-03-111-17/+3
| | | | llvm-svn: 203527
* X86: Enable ISel of 16-bit MOVBE instructions.Jim Grosbach2014-03-112-1/+9
| | | | | | | | | | | | | | | | | When the MOVBE instructions are available, use them for 16-bit endian swapping as well as for 32 and 64 bit. The patterns were already present on the instructions, but weren't being matched because the operation was unconditionally marked to 'Expand.' Change that to be conditional on whether the MOVBE instructions are available. Use 'rolw' to implement the in-register version (32 and 64 bit have the dedicated 'bswap' instruction for that). Patch by Louis Gerbarg <lgg@apple.com>. rdar://15479984 llvm-svn: 203524
* Follow up to r203488. Code clean up to eliminate a lot of copy+paste.Evan Cheng2014-03-111-215/+35
| | | | llvm-svn: 203520
* Remove incomplete commentMatt Arsenault2014-03-111-2/+0
| | | | llvm-svn: 203518
* Move trivial getter into header.Matt Arsenault2014-03-112-7/+4
| | | | llvm-svn: 203517
* Use .data() instead of &x[0]Matt Arsenault2014-03-111-2/+2
| | | | llvm-svn: 203516
* Fix indentationMatt Arsenault2014-03-111-9/+8
| | | | llvm-svn: 203515
* Fix non 2-space indentation.Matt Arsenault2014-03-111-73/+73
| | | | llvm-svn: 203514
* Module: Don't rename in getOrInsertFunction()Duncan P. N. Exon Smith2014-03-101-10/+0
| | | | | | | | | | | | | | | | | | | | | | | During LTO, user-supplied definitions of C library functions often exist. -instcombine uses Module::getOrInsertFunction() to get a handle on library functions (e.g., @puts, when optimizing @printf). Previously, Module::getOrInsertFunction() would rename any matching functions with local linkage, and create a new declaration. In LTO, this is the opposite of desired behaviour, as it skips by the user-supplied version of the library function and creates a new undefined reference which the linker often cannot resolve. After some discussing with Rafael on the list, it looks like it's undesired behaviour. If a consumer actually *needs* this behaviour, we should add new API with a more explicit name. I added two testcases: one specifically for the -instcombine behaviour and one for the LTO flow. <rdar://problem/16165191> llvm-svn: 203513
* When analyzing vectors of element type that require legalization,Raul E. Silvera2014-03-101-2/+3
| | | | | | | | | | | | | | | | | | the legalization cost must be included to get an accurate estimation of the total cost of the scalarized vector. The inaccurate cost triggered unprofitable SLP vectorization on 32-bit X86. Summary: Include legalization overhead when computing scalarization cost Reviewers: hfinkel, nadav CC: chandlerc, rnk, llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2992 llvm-svn: 203509
* Use discriminator information in sample profiles.Diego Novillo2014-03-101-40/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When the sample profiles include discriminator information, use the discriminator values to distinguish instruction weights in different basic blocks. This modifies the BodySamples mapping to map <line, discriminator> pairs to weights. Instructions on the same line but different blocks, will use different discriminator values. This, in turn, means that the blocks may have different weights. Other changes in this patch: - Add tests for positive values of line offset, discriminator and samples. - Change data types from uint32_t to unsigned and int and do additional validation. Reviewers: chandlerc CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2857 llvm-svn: 203508
* IR: Slightly more verbose error in VerifierJustin Bogner2014-03-101-2/+4
| | | | | | | | | | Extend the error message generated by the Verifier when an intrinsic name does not match the expected mangling to include the expected name. Simplifies debugging. Patch by Philip Reames! llvm-svn: 203490
* MemCpyOpt: When merging memsets also merge the trivial case of two memsets ↵Benjamin Kramer2014-03-101-0/+7
| | | | | | | | with the same destination. The testcase is from PR19092, but I think the bug described there is actually a clang issue. llvm-svn: 203489
* For functions with ARM target specific calling convention, when simplify-libcallEvan Cheng2014-03-102-48/+241
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | optimize a call to a llvm intrinsic to something that invovles a call to a C library call, make sure it sets the right calling convention on the call. e.g. extern double pow(double, double); double t(double x) { return pow(10, x); } Compiles to something like this for AAPCS-VFP: define arm_aapcs_vfpcc double @t(double %x) #0 { entry: %0 = call double @llvm.pow.f64(double 1.000000e+01, double %x) ret double %0 } declare double @llvm.pow.f64(double, double) #1 Simplify libcall (part of instcombine) will turn the above into: define arm_aapcs_vfpcc double @t(double %x) #0 { entry: %__exp10 = call double @__exp10(double %x) #1 ret double %__exp10 } declare double @__exp10(double) The pre-instcombine code works because calls to LLVM builtins are special. Instruction selection will chose the right calling convention for the call. However, the code after instcombine is wrong. The call to __exp10 will use the C calling convention. I can think of 3 options to fix this. 1. Make "C" calling convention just work since the target should know what CC is being used. This doesn't work because each function can use different CC with the "pcs" attribute. 2. Have Clang add the right CC keyword on the calls to LLVM builtin. This will work but it doesn't match the LLVM IR specification which states these are "Standard C Library Intrinsics". 3. Fix simplify libcall so the resulting calls to the C routines will have the proper CC keyword. e.g. %__exp10 = call arm_aapcs_vfpcc double @__exp10(double %x) #1 This works and is the solution I implemented here. Both solutions #2 and #3 would work. After carefully considering the pros and cons, I decided to implement #3 for the following reasons. 1. It doesn't change the "spec" of the intrinsics. 2. It's a self-contained fix. There are a couple of potential downsides. 1. There could be other places in the optimizer that is broken in the same way that's not addressed by this. 2. There could be other calling conventions that need to be propagated by simplify-libcall that's not handled. But for now, this is the fix that I'm most comfortable with. llvm-svn: 203488
* [mips] Implement NaCl sandboxing of loads, stores and SP changes:Sasa Stankovic2014-03-103-5/+123
| | | | | | | | | | * Add masking instructions before loads and stores (in MC layer). * Add masking instructions after SP changes (in MC layer). * Forbid loads, stores and SP changes in delay slots (in MI layer). Differential Revision: http://llvm-reviews.chandlerc.com/D2904 llvm-svn: 203484
* Make sure NVPTX doesn't emit symbol names that aren't valid in PTX.Eli Bendersky2014-03-102-16/+48
| | | | | | | | | | NVPTX, like the other backends, relies on generic symbol name sanitizing done by MCSymbol. However, the ptxas assembler is more stringent and disallows some additional characters in symbol names. See PR19099 for more details. llvm-svn: 203483
* llvm-c: expose unnamedaddr field of globalsTim Northover2014-03-101-0/+8
| | | | | | Patch by Manuel Jacob. llvm-svn: 203482
* Fix regression with -O0 for mips .Reed Kotler2014-03-101-0/+12
| | | | llvm-svn: 203469
* [C++11] Modernize the IR library a bit.Benjamin Kramer2014-03-105-67/+42
| | | | | | No functionality change. llvm-svn: 203465
* [mips][fp64] Add an implicit def to MFHC1 claiming that it reads the lower ↵Daniel Sanders2014-03-101-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 32-bits of 64-bit FPR Summary: This is a white lie to workaround a widespread bug in the -mfp64 implementation. The problem is that none of the 32-bit fpu ops mention the fact that they clobber the upper 32-bits of the 64-bit FPR. This allows MFHC1 to be scheduled on the wrong side of most 32-bit FPU ops. Fixing that requires a major overhaul of the FPU implementation which can't be done right now due to time constraints. MFHC1 is one of two affected instructions. These instructions are the only FPU instructions that don't read or write the lower 32-bits. We therefore pretend that it reads the bottom 32-bits to artificially create a dependency and prevent the scheduler changing the behaviour of the code. The other instruction is MTHC1 which will be fixed once I've have found a failing test case for it. The testcase is test-suite/SingleSource/UnitTests/Vector/simple.c when given TARGET_CFLAGS="-mips32r2 -mfp64 -mmsa". Reviewers: jacksprat, matheusalmeida Reviewed By: jacksprat Differential Revision: http://llvm-reviews.chandlerc.com/D2966 llvm-svn: 203464
* [mips] Assembly parser must invoke the target streamer to handle .set ↵Matheus Almeida2014-03-101-0/+1
| | | | | | reorder macro. llvm-svn: 203459
* AArch64: fix LowerCONCAT_VECTORS for new CodeGen.Tim Northover2014-03-101-10/+11
| | | | | | | | | | | | | | | The function was making too many assumptions about its input: 1. The NEON_VDUP optimisation was far too aggressive, assuming (I think) that the input would always be BUILD_VECTOR. 2. We were treating most unknown concats as legal (by returning Op rather than SDValue()). I think only concats of pairs of vectors are actually legal. http://llvm.org/PR19094 llvm-svn: 203450
* [C++11] Remove 'virtual' keyword from methods marked with 'override' keyword.Craig Topper2014-03-106-134/+127
| | | | llvm-svn: 203444
* [C++11] Remove 'virtual' keyword from methods marked with 'override' keyword.Craig Topper2014-03-105-22/+20
| | | | llvm-svn: 203442
* [AArch64] Fix a use of uninitialized memory introduced in r203125,Chandler Carruth2014-03-101-3/+3
| | | | | | | and caught by the MSan bootstrap build bot. This should hopefully get the bot green at long last. llvm-svn: 203441
* De-virtualize a method since it doesn't override anything and isn't ↵Craig Topper2014-03-101-1/+1
| | | | | | overridden itself. llvm-svn: 203440
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-1010-115/+114
| | | | | | class. llvm-svn: 203439
* [TTI] There is actually no realistic way to pop TTI implementations offChandler Carruth2014-03-108-36/+0
| | | | | | | | | | | | | | the stack of the analysis group because they are all immutable passes. This is made clear by Craig's recent work to use override systematically -- we weren't overriding anything for 'finalizePass' because there is no such thing. This is kind of a lame restriction on the API -- we can no longer push and pop things, we just set up the stack and run. However, I'm not invested in building some better solution on top of the existing (terrifying) immutable pass and legacy pass manager. llvm-svn: 203437
* [LCG] Ran clang-format over this too and it pointed out some fixes.Chandler Carruth2014-03-101-4/+6
| | | | llvm-svn: 203435
* [PM] While I'm here, fix a few other clang-format issues. Pulls someChandler Carruth2014-03-101-2/+4
| | | | | | lines under 80-columns, etc. llvm-svn: 203434
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-1031-414/+407
| | | | | | class. llvm-svn: 203433
* MC: Appease the buildbotsDavid Majnemer2014-03-101-2/+2
| | | | | | This is fallout from r203429. llvm-svn: 203430
* MC: Cleanup MCSectionMachO::ParseSectionSpecifierDavid Majnemer2014-03-101-77/+43
| | | | | | | | | Split by comma once instead of multiple times. Moving this upfront makes the rest of the code considerably simpler. No functional change. llvm-svn: 203429
* [Sparc] Add support for decoding 'swap' instruction.Venkatraman Govindaraju2014-03-092-1/+37
| | | | llvm-svn: 203424
* Fix inconsistent whitespace.Bob Wilson2014-03-091-1/+1
| | | | llvm-svn: 203423
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-0911-63/+60
| | | | | | class. llvm-svn: 203418
* StackColoring: Use range-based for loops.Benjamin Kramer2014-03-091-79/+47
| | | | | | No functionality change. llvm-svn: 203415
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