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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-03-11 01:38:53 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-03-11 01:38:53 +0000 |
| commit | 0211714ecb22d6e6f13a0c6681fb88b9365004dc (patch) | |
| tree | 752f66e1d3d8c2f935852d121dc7bce6aa8eed22 /llvm/lib | |
| parent | 3d9940213174bbc49696dd81adeac2cf1e77d763 (diff) | |
| download | bcm5719-llvm-0211714ecb22d6e6f13a0c6681fb88b9365004dc.tar.gz bcm5719-llvm-0211714ecb22d6e6f13a0c6681fb88b9365004dc.zip | |
R600: Calculate store mask instead of using switch.
llvm-svn: 203527
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/R600/AMDGPUISelLowering.cpp | 20 |
1 files changed, 3 insertions, 17 deletions
diff --git a/llvm/lib/Target/R600/AMDGPUISelLowering.cpp b/llvm/lib/Target/R600/AMDGPUISelLowering.cpp index 0fa8133edf2..8e19e66aaf3 100644 --- a/llvm/lib/Target/R600/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/R600/AMDGPUISelLowering.cpp @@ -630,17 +630,8 @@ SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op, unsigned MemEltBits = MemEltVT.getSizeInBits(); unsigned MemNumElements = MemVT.getVectorNumElements(); EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), MemVT.getSizeInBits()); - SDValue Mask; - switch(MemEltBits) { - case 8: - Mask = DAG.getConstant(0xFF, PackedVT); - break; - case 16: - Mask = DAG.getConstant(0xFFFF, PackedVT); - break; - default: - llvm_unreachable("Cannot lower this vector store"); - } + SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, PackedVT); + SDValue PackedValue; for (unsigned i = 0; i < MemNumElements; ++i) { EVT ElemVT = VT.getVectorElementType(); @@ -725,12 +716,7 @@ SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const { return SDValue(); - unsigned Mask = 0; - if (Load->getMemoryVT() == MVT::i8) { - Mask = 0xff; - } else if (Load->getMemoryVT() == MVT::i16) { - Mask = 0xffff; - } + unsigned Mask = (1 << Load->getMemoryVT().getSizeInBits()) - 1; SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(), DAG.getConstant(2, MVT::i32)); SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(), |
