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* Mips specific llvm assembler support for ALU instructions. This includesJack Carter2012-09-051-22/+367
| | | | | | | register support. Test case included. Contributer: Vladimir Medic llvm-svn: 163268
* Cleanup a few magic numbers.Chad Rosier2012-09-052-2/+2
| | | | llvm-svn: 163263
* Stop casting away const qualifier needlessly.Roman Divacky2012-09-0514-17/+17
| | | | llvm-svn: 163258
* [ms-inline asm] We only need one bit to represent the AsmDialect in theChad Rosier2012-09-052-11/+5
| | | | | | MachineInstr. llvm-svn: 163257
* Constify this properly. Found by gcc48 -Wcast-qual.Roman Divacky2012-09-051-4/+4
| | | | llvm-svn: 163256
* Mark checkSignature const, and in turn stop casting away const fromRoman Divacky2012-09-052-3/+3
| | | | | | ArchiveMemberHeader. Found by gcc48 -Wcast-qual. llvm-svn: 163255
* Constify SDNodeIterator an stop its only non-const user being cast strippedRoman Divacky2012-09-051-1/+1
| | | | | | of its constness. Found by gcc48 -Wcast-qual. llvm-svn: 163254
* Constify subtarget info properly so that we dont cast away the const inRoman Divacky2012-09-052-6/+6
| | | | | | the SubtargetInfoKV tables. Found by gcc48 -Wcast-qual. llvm-svn: 163251
* Use const properly so that we dont remove const qualifier from region and MIIRoman Divacky2012-09-053-13/+13
| | | | | | by casting. Found with gcc48. llvm-svn: 163247
* [ms-inline asm] Propagate the asm dialect into the MachineInstr representation.Chad Rosier2012-09-052-1/+19
| | | | llvm-svn: 163243
* Move the PPC TOC defs into the PPC64 InstrInfo file.Hal Finkel2012-09-052-3/+3
| | | | | | | | Since TOC is just defined for PPC64, move its definition to PPC64 td file. Patch by Adhemerval Zanella. llvm-svn: 163234
* [ms-inline asm] Enumerate the InlineAsm dialects and rename the nsdialect toChad Rosier2012-09-058-17/+19
| | | | | | inteldialect. llvm-svn: 163231
* Strip old MachineInstrs *after* we know we can put them back.Tim Northover2012-09-051-6/+6
| | | | | | | | Previous patch accidentally decided it couldn't convert a VFP to a NEON instruction after it had already destroyed the old one. Not a good move. llvm-svn: 163230
* Remove unused typedefs gcc4.8 warns about.Roman Divacky2012-09-052-2/+0
| | | | llvm-svn: 163225
* MCJIT: getPointerToFunction() references target address space.Jim Grosbach2012-09-053-2/+27
| | | | | | | Make sure to return a pointer into the target memory, not the local memory. Often they are the same, but we can't assume that. llvm-svn: 163217
* Switch BasicAliasAnalysis' cache to SmallDenseMap.Benjamin Kramer2012-09-051-9/+7
| | | | | | | | It relies on clear() being fast and the cache rarely has more than 1 or 2 elements, so give it an inline capacity and always shrink it back down in case it grows. DenseMap will grow to 64 buckets which makes clear() a lot slower. llvm-svn: 163215
* LLVM Bug Fix 13709: Remove needless lsr(Rp, #32) instruction access thePranav Bhandarkar2012-09-051-0/+35
| | | | | | | | | | | | | | | subreg_hireg of register pair Rp. * lib/Target/Hexagon/HexagonPeephole.cpp(PeepholeDoubleRegsMap): New DenseMap similar to PeepholeMap that additionally records subreg info too. (runOnMachineFunction): Record information in PeepholeDoubleRegsMap and copy propagate the high sub-reg of Rp0 in Rp1 = lsr(Rp0, #32) to the instruction Rx = COPY Rp1:logreg_subreg. * test/CodeGen/Hexagon/remove_lsr.ll: New test. llvm-svn: 163214
* [asan] fix lintKostya Serebryany2012-09-051-1/+1
| | | | llvm-svn: 163205
* Fixed the DAG combiner to better handle the folding of AND nodes for vector ↵Silviu Baranga2012-09-051-1/+11
| | | | | | types. The previous code was making the assumption that the length of the bitmask returned by isConstantSplat was equal to the size of the vector type. Now we first make sure that the splat value has at least the length of the vector lane type, then we only use as many fields as we have available in the splat value. llvm-svn: 163203
* [asan] extend the blacklist functionality to handle global-init. Patch by ↵Kostya Serebryany2012-09-053-1/+11
| | | | | | Reid Watson llvm-svn: 163199
* Remove some of the patterns added in r163196. Increasing the complexity on ↵Craig Topper2012-09-051-42/+2
| | | | | | insert_subvector into undef accomplishes the same thing. llvm-svn: 163198
* Add patterns for integer forms of VINSERTF128/VINSERTI128 folded with loads. ↵Craig Topper2012-09-051-4/+76
| | | | | | Also add patterns to turn subvector inserts with loads to index 0 of an undef into VMOVAPS. llvm-svn: 163196
* Add a FIXME that assumes we maintain backward compatibility until the next ↵Chad Rosier2012-09-051-0/+1
| | | | | | major release. llvm-svn: 163195
* Reorder the comments of EmitExceptionTable.Logan Chien2012-09-051-20/+20
| | | | llvm-svn: 163194
* Fix UseInitArray option for MIPS target.Logan Chien2012-09-051-0/+1
| | | | llvm-svn: 163193
* Convert vextracti128/vextractf128 intrinsics to extract_subvector at DAG ↵Craig Topper2012-09-052-29/+66
| | | | | | build time. Similar was previously done for vinserti128/vinsertf128. Add patterns for folding these extract_subvectors with stores. llvm-svn: 163192
* Remove redundant semicolons to fix -pedantic-errors build.Richard Smith2012-09-051-2/+2
| | | | llvm-svn: 163190
* Fix function name per coding standard.Chad Rosier2012-09-054-10/+10
| | | | llvm-svn: 163187
* [ms-inline asm] Add support for the nsdialect keyword in the BitcodeChad Rosier2012-09-052-2/+28
| | | | | | Reader/Writer. llvm-svn: 163185
* [ms-inline asm] Add the nsdialect keyword to the lexer.Chad Rosier2012-09-051-0/+1
| | | | llvm-svn: 163184
* [ms-inline asm] Emit the (new) inline asm Non-Standard Dialect attribute.Chad Rosier2012-09-053-3/+9
| | | | llvm-svn: 163181
* Make provenance checking conservative in cases whenDan Gohman2012-09-041-37/+42
| | | | | | | | pointers-to-strong-pointers may be in play. These can lead to retains and releases happening in unstructured ways, foiling the optimizer. This fixes rdar://12150909. llvm-svn: 163180
* BypassSlowDivision: Assign to reference, don't copy the object.Jakub Staszak2012-09-041-2/+2
| | | | llvm-svn: 163179
* Search the whole instruction for tied operands.Jakob Stoklund Olesen2012-09-041-2/+1
| | | | | | | Implicit uses can be dynamically tied to defs. This will soon be used for predicated instructions on ARM. llvm-svn: 163177
* [ms-inline asm] Add the inline assembly dialect, AsmDialect, to the InlineAsmChad Rosier2012-09-043-13/+23
| | | | | | class. llvm-svn: 163175
* [ms-inline asm] Remove the Inline Asm Non-Standard Dialect attribute. ThisChad Rosier2012-09-044-6/+0
| | | | | | | implementation does not co-exist well with how the sideeffect and alignstack attributes are handled. The reverts r161641. llvm-svn: 163174
* Fix my previous patch (r163164). It does now what it is supposed to do:Jakub Staszak2012-09-041-1/+0
| | | | | | Doesn't set MadeChange to TRUE if BypassSlowDivision doesn't change anything. llvm-svn: 163165
* Return false if BypassSlowDivision doesn't change anything.Jakub Staszak2012-09-041-33/+34
| | | | | | | | | | Also a few minor changes: - use pre-inc instead of post-inc - use isa instead of dyn_cast - 80 col - trailing spaces llvm-svn: 163164
* Typo.Jakob Stoklund Olesen2012-09-041-1/+1
| | | | llvm-svn: 163154
* Actually use the MachineOperand field for isRegTiedToDefOperand().Jakob Stoklund Olesen2012-09-041-103/+0
| | | | | | | | | | The MachineOperand::TiedTo field was maintained, but not used. This patch enables it in isRegTiedToDefOperand() and isRegTiedToUseOperand() which are the actual functions use by the register allocator. llvm-svn: 163153
* Move tie checks into MachineVerifier::visitMachineOperand.Jakob Stoklund Olesen2012-09-041-36/+26
| | | | llvm-svn: 163152
* Allow tied uses and defs in different orders.Jakob Stoklund Olesen2012-09-041-30/+91
| | | | | | | | | | | | | | | | After much agonizing, use a full 4 bits of precious MachineOperand space to encode this. This uses existing padding, and doesn't grow MachineOperand beyond its current 32 bytes. This allows tied defs among the first 15 operands on a normal instruction, just like the current MCInstrDesc constraint encoding. Inline assembly needs to be able to tie more than the first 15 operands, and gets special treatment. Tied uses can appear beyond 15 operands, as long as they are tied to a def that's in range. llvm-svn: 163151
* Generic Bypass Slow DivPreston Gurd2012-09-048-3/+281
| | | | | | | | | | | | | | | | | | | | | | | - CodeGenPrepare pass for identifying div/rem ops - Backend specifies the type mapping using addBypassSlowDivType - Enabled only for Intel Atom with O2 32-bit -> 8-bit - Replace IDIV with instructions which test its value and use DIVB if the value is positive and less than 256. - In the case when the quotient and remainder of a divide are used a DIV and a REM instruction will be present in the IR. In the non-Atom case they are both lowered to IDIVs and CSE removes the redundant IDIV instruction, using the quotient and remainder from the first IDIV. However, due to this optimization CSE is not able to eliminate redundant IDIV instructions because they are located in different basic blocks. This is overcome by calculating both the quotient (DIV) and remainder (REM) in each basic block that is inserted by the optimization and reusing the result values when a subsequent DIV or REM instruction uses the same operands. - Test cases check for the presents of the optimization when calculating either the quotient, remainder, or both. Patch by Tyler Nowicki! llvm-svn: 163150
* Porting Hexagon MI Scheduler to the new API.Sergei Larin2012-09-048-1/+1377
| | | | | | | Change current Hexagon MI scheduler to use new converging scheduler. Integrates DFA resource model into it. llvm-svn: 163137
* Patch to implement UMLAL/SMLAL instructions for the ARM architectureArnold Schwaighofer2012-09-045-17/+251
| | | | | | | | | | | This patch corrects the definition of umlal/smlal instructions and adds support for matching them to the ARM dag combiner. Bug 12213 Patch by Yin Ma! llvm-svn: 163136
* This patch optimizes shuffle instruction - generates 2 instructions instead ↵Elena Demikhovsky2012-09-041-16/+17
| | | | | | | | | | | | | | | | | | | | of 4. Since this specific shuffle is widely used in many workloads we have ~10% performance on them. shufflevector <8 x float> %A, <8 x float> %B, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14> vmovaps (%rdx), %ymm0 vshufps $8, %ymm0, %ymm0, %ymm0 vmovaps (%rcx), %ymm1 vshufps $8, %ymm0, %ymm1, %ymm1 vunpcklps %ymm0, %ymm1, %ymm0 vmovaps (%rcx), %ymm0 vmovsldup (%rdx), %ymm1 vblendps $85, %ymm0, %ymm1, %ymm0 llvm-svn: 163134
* LICM may hoist an instruction with undefined behavior above a trap.Nadav Rotem2012-09-041-7/+30
| | | | | | | | | | Scan the body of the loop and find instructions that may trap. Use this information when deciding if it is safe to hoist or sink instructions. Notice that we can optimize the search of instructions that may throw in the case of nested loops. rdar://11518836 llvm-svn: 163132
* Fix Android build of gtest and lib/Support.Evgeniy Stepanov2012-09-042-2/+2
| | | | llvm-svn: 163131
* Add support for fetching inlining context (stack of source code locations)Alexey Samsonov2012-09-048-79/+279
| | | | | | | | | | | by instruction address from DWARF. Add --inlining flag to llvm-dwarfdump to demonstrate and test this functionality, so that "llvm-dwarfdump --inlining --address=0x..." now works much like "addr2line -i 0x...", provided that the binary has debug info (Clang's -gline-tables-only *is* enough). llvm-svn: 163128
* Be conservative about allocations that may alias the accessed pointer.Bob Wilson2012-09-041-0/+3
| | | | | | | | | | If an allocation has a must-alias relation to the access pointer, we treat it as a Def. Otherwise, without this check, the code here was just skipping over the allocation call and ignoring it. I noticed this by inspection and don't have a specific testcase that it breaks, but it seems like we need to treat a may-alias allocation as a Clobber. llvm-svn: 163127
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