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| author | Tim Northover <Tim.Northover@arm.com> | 2012-09-05 18:37:53 +0000 |
|---|---|---|
| committer | Tim Northover <Tim.Northover@arm.com> | 2012-09-05 18:37:53 +0000 |
| commit | c8d867d42deebdee34d984f0b9884fcb336a3429 (patch) | |
| tree | df1155187544a3a78f386ae4962a4aed28de9b5f /llvm/lib | |
| parent | 100b59c0a0d8be80ac88b6f26e0e1e83bd23745a (diff) | |
| download | bcm5719-llvm-c8d867d42deebdee34d984f0b9884fcb336a3429.tar.gz bcm5719-llvm-c8d867d42deebdee34d984f0b9884fcb336a3429.zip | |
Strip old MachineInstrs *after* we know we can put them back.
Previous patch accidentally decided it couldn't convert a VFP to a
NEON instruction after it had already destroyed the old one. Not a
good move.
llvm-svn: 163230
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index dc4b67a8324..f8e554fcbfd 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -3479,9 +3479,6 @@ ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const { DstReg = MI->getOperand(0).getReg(); SrcReg = MI->getOperand(1).getReg(); - for (unsigned i = MI->getDesc().getNumOperands(); i; --i) - MI->RemoveOperand(i-1); - DReg = getCorrespondingDRegAndLane(TRI, DstReg, Lane); // If we insert both a novel <def> and an <undef> on the DReg, we break @@ -3491,6 +3488,9 @@ ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const { if (!MI->definesRegister(DReg, TRI) && !MI->readsRegister(DReg, TRI)) break; + for (unsigned i = MI->getDesc().getNumOperands(); i; --i) + MI->RemoveOperand(i-1); + // Convert to %DDst = VSETLNi32 %DDst, %RSrc, Lane, 14, %noreg (; imps) // Again DDst may be undefined at the beginning of this instruction. MI->setDesc(get(ARM::VSETLNi32)); @@ -3512,9 +3512,6 @@ ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const { DstReg = MI->getOperand(0).getReg(); SrcReg = MI->getOperand(1).getReg(); - for (unsigned i = MI->getDesc().getNumOperands(); i; --i) - MI->RemoveOperand(i-1); - unsigned DstLane = 0, SrcLane = 0, DDst, DSrc; DDst = getCorrespondingDRegAndLane(TRI, DstReg, DstLane); DSrc = getCorrespondingDRegAndLane(TRI, SrcReg, SrcLane); @@ -3526,6 +3523,9 @@ ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const { if (!MI->definesRegister(DDst, TRI) && !MI->readsRegister(DDst, TRI)) break; + for (unsigned i = MI->getDesc().getNumOperands(); i; --i) + MI->RemoveOperand(i-1); + if (DSrc == DDst) { // Destination can be: // %DDst = VDUPLN32d %DDst, Lane, 14, %noreg (; implicits) |
