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* Also need to handle invalid imod values for CPS2p.Johnny Chen2011-03-251-4/+11
| | | | | | rdar://problem/9186136 llvm-svn: 128283
* Fix for -pre-RA-sched=source.Andrew Trick2011-03-251-0/+2
| | | | | | | Yet another case of unchecked NULL node (for physreg copy). May fix PR9509. llvm-svn: 128266
* No functionality change, just adjust some whitespace for coding style ↵Nick Lewycky2011-03-251-2/+2
| | | | | | compliance. llvm-svn: 128257
* No functionality change. Fix up some whitespace and switch out "" for '' whenNick Lewycky2011-03-251-3/+3
| | | | | | printing a single character. llvm-svn: 128256
* Ignore special ARM allocation hints for unexpected register classes.Jakob Stoklund Olesen2011-03-252-0/+5
| | | | | | | | | Add an assertion to linear scan to prevent it from allocating registers outside the register class. <rdar://problem/9183021> llvm-svn: 128254
* Modify the wrong logic in the assert of DisassembleThumb2LdStDual() (the ↵Johnny Chen2011-03-251-9/+9
| | | | | | | | register classes were changed), modify the comment to be up-to-date, and add a test case for A8.6.66 LDRD (immediate) Encoding T1. llvm-svn: 128252
* Suppress an unused variable warning in -asserts buildsMatt Beaumont-Gay2011-03-241-0/+1
| | | | llvm-svn: 128244
* Handle the added VBICiv*i* NEON instructions, too.Johnny Chen2011-03-241-2/+7
| | | | llvm-svn: 128243
* Plug a leak by ThumbDisassembler::getInstruction(), thanks to Benjamin Kramer!Johnny Chen2011-03-241-3/+1
| | | | llvm-svn: 128241
* T2 Load/Store Multiple:Johnny Chen2011-03-241-1/+1
| | | | | | | These instructions were changed to not embed the addressing mode within the MC instructions We also need to update the corresponding assert stmt. Also add a test case. llvm-svn: 128240
* Plug a leak in the arm disassembler and put the tests back.Benjamin Kramer2011-03-241-3/+2
| | | | llvm-svn: 128238
* Add asm parsing support w/ testcases for strex/ldrex family of instructionsBruno Cardoso Lopes2011-03-248-61/+111
| | | | llvm-svn: 128236
* ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder ↵Johnny Chen2011-03-241-1/+1
| | | | | | | | | was fooled. Set the encoding bits to {0,?,?,0}, not 0. Plus delegate the disassembly of ADR to the more generic ADDri/SUBri instructions, and add a test case for that. llvm-svn: 128234
* Keep track of directory namd and fIx regression caused by Rafael's patch ↵Devang Patel2011-03-242-12/+29
| | | | | | | | r119613. A better approach would be to move source id handling inside MC. llvm-svn: 128233
* Clean up assembly statement separator support.Jim Grosbach2011-03-243-8/+19
| | | | | | | | The MC asm lexer wasn't honoring a non-default (anything but ';') statement separator. Fix that, and generalize a bit to support multi-character statement separators. llvm-svn: 128227
* The r118201 added support for VORR (immediate). Update ↵Johnny Chen2011-03-241-0/+16
| | | | | | | | ARMDisassemblerCore.cpp to disassemble the VORRiv*i* instructions properly within the DisassembleN1RegModImmFrm() function. Add a test case. llvm-svn: 128226
* Add comments to the handling of opcode CPS3p to reject invalid instruction ↵Johnny Chen2011-03-241-0/+2
| | | | | | | | encoding, a test case of invalid CPS3p encoding and one for invalid VLDMSDB due to regs out of range. llvm-svn: 128220
* revert r128199 until it can be made to work with Frontend/dependency-gen.c.Andrew Trick2011-03-241-5/+9
| | | | llvm-svn: 128218
* Debug intrinsics must be skipped at the beginning and ends of blocks, lest theyCameron Zwarich2011-03-241-2/+6
| | | | | | affect the generated code. llvm-svn: 128217
* It is enough for the CallInst to have no uses to be made a tail call with a retCameron Zwarich2011-03-241-1/+1
| | | | | | void; it doesn't need to have a void type. llvm-svn: 128212
* s/UpdateDT/ModifiedDT/gDevang Patel2011-03-241-8/+8
| | | | llvm-svn: 128211
* Target/X86: [PR8777][PR8778] Tweak alloca/chkstk for Windows targets.NAKAMURA Takumi2011-03-243-62/+106
| | | | | FIXME: Some cleanups would be needed. llvm-svn: 128206
* Nasty bug in ARMBaseInstrInfo::produceSameValue(). The MachineConstantPoolEntryEvan Cheng2011-03-241-5/+12
| | | | | | | | | | | | entries being compared may not be ARMConstantPoolValue. Without checking whether they are ARMConstantPoolValue first, and if the stars and moons are aligned properly, the equality test may return true (when the first few words of two Constants' values happen to be identical) and very bad things can happen. rdar://9125354 llvm-svn: 128203
* Remove all uses of PATH_MAX and MAXPATHLEN from PathV2.Michael J. Spencer2011-03-241-9/+5
| | | | llvm-svn: 128199
* Do early taildup of ret in CodeGenPrepare for potential tail calls that have aCameron Zwarich2011-03-241-17/+37
| | | | | | void return type. This fixes PR9487. llvm-svn: 128197
* Use an early return instead of a long if block.Cameron Zwarich2011-03-241-51/+51
| | | | llvm-svn: 128196
* When UpdateDT is set, DT is invalid, which could cause problems when trying toCameron Zwarich2011-03-241-2/+3
| | | | | | use it later. I couldn't make a test that hits this with the current code. llvm-svn: 128195
* Check for TLI so that -codegenprepare can be used from opt.Cameron Zwarich2011-03-241-0/+3
| | | | llvm-svn: 128194
* CPS3p: Let's reject impossible imod values by returning false from the ↵Johnny Chen2011-03-241-0/+3
| | | | | | | | | | | | | | | | | | | | | | | DisassembleMiscFrm() function. Fixed rdar://problem/9179416 ARM disassembler crash: "Unknown imod operand" (fuzz testing) Opcode=98 Name=CPS3p Format=ARM_FORMAT_MISCFRM(26) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 1: 1: 1| 0: 0: 0: 1| 0: 0: 0: 0| 0: 0: 1: 0| 0: 0: 0: 1| 1: 1: 0: 0| 1: 0: 0: 1| 0: 0: 1: 1| ------------------------------------------------------------------------------------------------- Before: cpsUnknown imod operand UNREACHABLE executed at /Volumes/data/lldb/llvm/lib/Target/ARM/InstPrinter/../ARMBaseInfo.h:123! After: /Volumes/data/Radar/9179416/mc-input-arm.txt:1:1: warning: invalid instruction encoding 0x93 0x1c 0x2 0xf1 ^ llvm-svn: 128192
* Load/Store Multiple:Johnny Chen2011-03-241-4/+4
| | | | | | | These instructions were changed to not embed the addressing mode within the MC instructions We also need to update the corresponding assert stmt. Also add two test cases. llvm-svn: 128191
* STRT and STRBT was incorrectly tagged as IndexModeNone during the ↵Johnny Chen2011-03-241-2/+2
| | | | | | | | refactorings (r119821). We now tag them as IndexModePost. llvm-svn: 128189
* The r128103 fix to cope with the removal of addressing modes from the MC ↵Johnny Chen2011-03-241-2/+7
| | | | | | | | | | instructions were incomplete. The assert stmt needs to be updated and the operand index incrment is wrong. Fix the bad logic and add some sanity checking to detect bad instruction encoding; and add a test case. llvm-svn: 128186
* Runtime dylib simple ARM 24-bit branch relocation support.Jim Grosbach2011-03-231-14/+49
| | | | llvm-svn: 128184
* Enable GlobalMerge on darwin.Devang Patel2011-03-231-6/+0
| | | | llvm-svn: 128183
* Revert r128175.Andrew Trick2011-03-231-73/+4
| | | | | | I'm backing this out for the second time. It was supposed to be fixed by r128164, but the mingw self-host must be defeating the fix. llvm-svn: 128181
* Cmp peephole optimization isn't always safe for signed arithmetics.Evan Cheng2011-03-231-3/+43
| | | | | | | | | | | | | | | | | | | | | int tries = INT_MAX; while (tries > 0) { tries--; } The check should be: subs r4, #1 cmp r4, #0 bgt LBB0_1 The subs can set the overflow V bit when r4 is INT_MAX+1 (which loop canonicalization apparently does in this case). cmp #0 would have cleared it while not changing the N and Z bits. Since BGT is dependent on the V bit, i.e. (N == V) && !Z, it is not safe to eliminate the cmp #0. rdar://9172742 llvm-svn: 128179
* PR9535: add support for splitting and scalarizing vector ISD::FP_ROUND.Eli Friedman2011-03-232-60/+30
| | | | | | Also cleaning up some duplicated code while I'm here. llvm-svn: 128176
* Reapply Eli's r127852 now that the pre-RA scheduler can spill EFLAGS.Andrew Trick2011-03-231-4/+73
| | | | | | (target-specific branchless method for double-width relational comparisons on x86) llvm-svn: 128175
* Split out relocation resolution into target-specific bits.Jim Grosbach2011-03-231-3/+71
| | | | llvm-svn: 128173
* The high bit of a Thumb2 ADR's offset is stored in bit 26, not bit 25.Owen Anderson2011-03-231-1/+1
| | | | | | This fixes 464.h264ref with the integrated assembler. llvm-svn: 128172
* Fix double-free of Module.Jim Grosbach2011-03-231-1/+0
| | | | | | | | The ExecutionEngine constructor already added the module, so there's no need to call addModule() directly. Doing so causes a double-free of the Module at program termination. llvm-svn: 128171
* Fix a bug introduced by my patch yesterday: BL is a 4-byte instructions like ↵Owen Anderson2011-03-231-3/+2
| | | | | | BLX, rather than a 2-byte instruction like B. llvm-svn: 128169
* Ensure that def-side physreg copies are scheduled above any other usesAndrew Trick2011-03-231-0/+9
| | | | | | | | | so the scheduler can't create new interferences on the copies themselves. Prior to this fix the scheduler could get stuck in a loop creating copies. Fixes PR9509. llvm-svn: 128164
* whitespaceAndrew Trick2011-03-231-2/+2
| | | | llvm-svn: 128163
* Start of relocation resolution for the runtime dyld library.Jim Grosbach2011-03-231-21/+130
| | | | llvm-svn: 128161
* Make sure to report any errors from the runtime dyld.Jim Grosbach2011-03-231-1/+2
| | | | llvm-svn: 128160
* Don't coalesce identical DBG_VALUE instructions prematurely.Jakob Stoklund Olesen2011-03-231-3/+1
| | | | | | | | Each of these instructions may have a RegsClobberInsn entry that can't be ignored. Consecutive ranges are coalesced later when DwarfDebug::emitDebugLoc merges entries. llvm-svn: 128155
* PTX: Improve support for 64-bit addressingJustin Holewinski2011-03-233-21/+72
| | | | | | | | | - Fix bug in ADDRrr/ADDRri/ADDRii selection for 64-bit addresses - Add comparison selection for i64 - Add zext selection for i32 -> i64 - Add shl/shr/sha support for i64 llvm-svn: 128153
* Revert r128140 for now.Anders Carlsson2011-03-231-33/+0
| | | | llvm-svn: 128149
* Fix PR9464 by correcting some math that just happened to be right in most casesCameron Zwarich2011-03-231-11/+10
| | | | | | that were hit in practice. llvm-svn: 128146
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