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* LowerTypeTests: Fix non-determinism in code that handles icall branch funnels.Peter Collingbourne2018-05-051-13/+26
| | | | | | | | | This was exposed by enabling expensive checks, which causes llvm::sort to sort randomly. Differential Revision: https://reviews.llvm.org/D45901 llvm-svn: 331573
* [LTO] Allow pass remarks with hotness to be set when emitting to stderrTeresa Johnson2018-05-041-2/+2
| | | | | | | | | | | | | | | | | | | | | Summary: Set setDiagnosticsHotnessRequested before the early exit check for a diagnostic output file, so that pass remarks with hotness works when emitting pass remarks to stderr (e.g. via -pass-remarks=.). Also fix the llvm-lto2 diagnistic handler so that it only calls exit(1) when the diagnistic is an error type. Otherwise the new test invocation of llvm-lto2 with -pass-remarks causes it to fail. The new code is consistent with the diagnostic handler elsewhere (e.g. on the LLVMContext). Reviewers: pcc, davide Subscribers: fhahn, mehdi_amini, llvm-commits, inglorion Differential Revision: https://reviews.llvm.org/D46387 llvm-svn: 331569
* Mapping SDNode flags to MachineInstr flagsMichael Berg2018-05-041-1/+26
| | | | | | | | | | | | | | Summary: Providing the glue to map SDNode fast math sub flags to MachineInstr fast math sub flags. Reviewers: spatel, arsenm, wristow Reviewed By: spatel Subscribers: wdng Differential Revision: https://reviews.llvm.org/D46447 llvm-svn: 331567
* AMDGPU/NFC: Update D16PreservesUnusedBits description based Tony Tye's commentsKonstantin Zhuravlyov2018-05-041-1/+3
| | | | llvm-svn: 331564
* [LICM] Compute a must execute property for the prefix of the header as we goPhilip Reames2018-05-041-3/+14
| | | | | | | | Computing this property within the existing walk ensures that the cost is linear with the size of the block. If we did this from within isGuaranteedToExecute, it would be quadratic without some very fancy caching. This allows us to reliably catch a hoistable instruction within a header which may throw at some point *after* our hoistable instruction. It doesn't do anything for non-header cases, but given how common single block loops are, this seems very worthwhile. llvm-svn: 331557
* AMDGPU/NFC: Fix formatting for 900, 902 ISA Version featuresKonstantin Zhuravlyov2018-05-041-4/+2
| | | | llvm-svn: 331553
* AMDGPU: Add D16 instructions preserve unused bits featureKonstantin Zhuravlyov2018-05-046-9/+27
| | | | | | | | | - Predicate D16 patterns on this new feature - Added this new feature to gfx900/2/4 Differential Revision: https://reviews.llvm.org/D46366 llvm-svn: 331551
* [MachineLICM] Debug intrinsics shouldn't affect hoist decisionsGeoff Berry2018-05-041-0/+4
| | | | | | | | | | | | | | | | Summary: When checking if an instruction stores to a given frame index, check that the instruction can write to memory before looking at the memory operands list to avoid e.g. DBG_VALUE instructions that reference a frame index preventing a load from that index from being hoisted. Reviewers: dblaikie, MatzeB, qcolombet, reames, javed.absar Subscribers: mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D46284 llvm-svn: 331549
* [ObjCARC] Account for catchswitch in bitcast insertionShoaib Meenai2018-05-041-4/+17
| | | | | | | | | | | | | A catchswitch is both a pad and a terminator, meaning it must be the only non-phi instruction in its basic block. When we're inserting a bitcast in the incoming basic block for a phi, if that incoming block is a catchswitch, we should go up the dominator tree to find a valid insertion point rather than attempting to insert before the catchswitch (which would result in invalid IR). Differential Revision: https://reviews.llvm.org/D46412 llvm-svn: 331548
* Fast Math Flag mapping into SDNodeMichael Berg2018-05-045-15/+18
| | | | | | | | | | | | | | Summary: Adding support for Fast flags in the SDNode to leverage fast math sub flag usage. Reviewers: spatel, arsenm, jbhateja, hfinkel, escha, qcolombet, echristo, wristow, javed.absar Reviewed By: spatel Subscribers: llvm-commits, rampitec, nhaehnle, tstellar, FarhanaAleen, nemanjai, javed.absar, jbhateja, hfinkel, wdng Differential Revision: https://reviews.llvm.org/D45710 llvm-svn: 331547
* [X86] Add WriteEMMS scheduler classSimon Pilgrim2018-05-0412-34/+15
| | | | | | Filled in the missing values from Btver2 SoG or Agner llvm-svn: 331546
* [X86] Finish splitting WriteVecShift and WriteVecIMul to remove InstRW ↵Simon Pilgrim2018-05-0411-103/+44
| | | | | | overrides. llvm-svn: 331543
* [LoopIdiomRecognize] Don't create an IRBuilder just to call getTrue/getFalse.Craig Topper2018-05-041-2/+2
| | | | | | We can call the methods in ConstantInt directly. We just need a context. llvm-svn: 331542
* DwarfCompileUnit: Fix another assertion failure on malformed inputAdrian Prantl2018-05-042-1/+2
| | | | | | | | that is not rejected by the Verifier. Thanks to Björn Pettersson for providing a reproducer! llvm-svn: 331535
* [llvm-exegesis] Fix pfm counter names for BDW.Clement Courbet2018-05-041-8/+8
| | | | | | | | | | | | Summary: They are not consistent with other microarchitectures. Reviewers: gchatelet Subscribers: tschuett, llvm-commits Differential Revision: https://reviews.llvm.org/D46434 llvm-svn: 331532
* [X86] Cleanup SchedWriteFMA classes and use X86SchedWriteWidths directly.Simon Pilgrim2018-05-0412-82/+80
| | | | | | Rename scalar and XMM versions, this is to match/simplify an upcoming change to split MUL/DIV/SQRT scalar/xmm/ymm/zmm classes. llvm-svn: 331531
* [Hexagon] Remove leftover debugging code after r331527Krzysztof Parzyszek2018-05-041-1/+0
| | | | llvm-svn: 331528
* [Hexagon] Handle non-immediate constants in HexagonSplitDoubleKrzysztof Parzyszek2018-05-042-24/+28
| | | | llvm-svn: 331527
* [mips] Correct the predicates of sign extension instructionsSimon Dardis2018-05-044-29/+5
| | | | | | | | | | And eliminatw the duplication of those instructions for microMIPS32r6. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46117 llvm-svn: 331526
* [X86] Add WriteVecMOVMSKY scheduler classSimon Pilgrim2018-05-0411-40/+48
| | | | llvm-svn: 331525
* [AArch64] Custom Lower MULLH{S,U} for v16i8, v8i16, and v4i32Adhemerval Zanella2018-05-042-2/+89
| | | | | | | | | | | | | | This patch adds a custom lowering for ISD::MULH{S,U} used on divide by constant optimization (DAGCombiner::BuildSDIV and DAGCombiner::BuildUDIV). New patterns for smull and umull are added, so AArch64ISD::{S,U}MULL can be correctly lowered to smull2 and umull2. Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D46009 llvm-svn: 331522
* [Hexagon] Skip reserved physical registers when updating livenessKrzysztof Parzyszek2018-05-041-1/+8
| | | | llvm-svn: 331518
* [X86] Add SchedWriteFRnd fp rounding scheduler classesSimon Pilgrim2018-05-0413-164/+67
| | | | | | | | Split off from SchedWriteFAdd for fp rounding/bit-manipulation instructions. Fixes an issue on btver2 which only had the ymm version using the JSTC pipe instead of JFPA. llvm-svn: 331515
* [SelectionDAG] Refactor code by adding RegsForValue::getRegsAndSizes(). NFCIBjorn Pettersson2018-05-042-40/+43
| | | | | | | | | | | | | | | | | | Summary: Added a helper method in RegsForValue to get a list with all the <RegNumber, RegSize> pairs that we want to iterate over in SelectionDAGBuilder::EmitFuncArgumentDbgValue and in SelectionDAGBuilder::visitIntrinsicCall. Reviewers: vsk Reviewed By: vsk Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D46360 llvm-svn: 331510
* [RegUsageInfoCollector] Bugfix for handling of register aliases.Jonas Paulsson2018-05-041-7/+6
| | | | | | | | | | | | | | | | | Don't assume the alias of a defined reg is always already in the set. As the test case in https://bugs.llvm.org/show_bug.cgi?id=36587 discovered, it is wrong to assume that all the aliases of the defined register in the *current function* is already present in the UsedPhysRegsMask. This patch changes this so that any definition in the current function of a phys-reg always results in all its aliases inserted into the set of defined registers. Review: Quentin Colombet https://reviews.llvm.org/D45157 llvm-svn: 331509
* [IRCE] Fix misuse of dyn_cast which leads to UBMax Kazantsev2018-05-041-2/+3
| | | | llvm-svn: 331508
* [MachineCSE] Rewrite a loop checking if a block is in a set of blocks ↵Michael Zolotukhin2018-05-041-7/+5
| | | | | | | | | | | | | | | | | | without using a set. NFC. Summary: Using a set is unnecessary here an in some cases (see e.g. PR37277) takes significant amount of time to just insert values into it. In this particular case all we need is just to check if we find the block we are looking for or not. Reviewers: davide Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D46411 llvm-svn: 331502
* [LoopIdiomRecognize] Replace more unchecked dyn_casts with cast.Craig Topper2018-05-041-4/+4
| | | | | | Two of these are immediately dereferenced on the next line. The other two are passed immediately to the IRBuilder constructor which can't handle a nullptr. llvm-svn: 331500
* [LoopIdiomRecognize] Use a regular array instead of a SmallVector and ↵Craig Topper2018-05-041-2/+1
| | | | | | explicit ArrayRef. llvm-svn: 331499
* [LoopIdiomRecognize] Turn two uncheck dyn_casts into regular casts.Craig Topper2018-05-041-2/+2
| | | | | | These are casts on users of a PHINode to Instruction. I think since PHINode is an Instruction any users would also be Instructions. At least a cast will give us an assertion if its wrong. llvm-svn: 331498
* AMDGPU: Make getSubRegFromChannel a static member of AMDGPURegisterInfoTom Stellard2018-05-035-9/+9
| | | | | | | | | | | | | | | | Summary: This makes is possible to have R600RegisterInfo and SIRegisterInfo not inherit from AMDGPURegisterInfo. Reviewers: arsenm, nhaehnle Reviewed By: arsenm Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D46280 llvm-svn: 331490
* [X86] Add WriteDPPD/WriteDPPS dot product scheduler classesSimon Pilgrim2018-05-0311-232/+42
| | | | llvm-svn: 331489
* [X86][Znver1] Use SchedAlias to tag microcoded scheduler classesSimon Pilgrim2018-05-031-32/+30
| | | | | | | | Avoids extra entries in the class tables. Found a typo that missed the MMX_PHSUBSW instruction. llvm-svn: 331488
* Fix include of config.h that was incorrectly changed in r331184Justin Bogner2018-05-031-1/+1
| | | | | | | | | The RWMutex implementation depends on config.h macros (specifically HAVE_PTHREAD_H and HAVE_PTHREAD_RWLOCK_INIT), so we need to be including it and not just llvm-config.h here or we fall back to a much slower implementation. llvm-svn: 331487
* [InstCombine] refine select-of-constants to bitwise opsSanjay Patel2018-05-031-57/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add logic for the special case when a cmp+select can clearly be reduced to just a bitwise logic instruction, and remove an over-reaching chunk of general purpose bit magic. The primary goal is to remove cases where we are not improving the IR instruction count when doing these select transforms, and in all cases here that is true. In the motivating 3-way compare tests, there are further improvements because we can combine/propagate select values (not sure if that belongs in instcombine, but it's there for now). DAGCombiner has folds to turn some of these selects into bit magic, so there should be no difference in the end result in those cases. Not all constant combinations are handled there yet, however, so it is possible that some targets will see more cmov/csel codegen with this change in IR canonicalization. Ideally, we'll go further to *not* turn selects into multiple logic/math ops in instcombine, and we'll canonicalize to selects. But we should make sure that this step does not result in regressions first (and if it does, we should fix those in the backend). The general direction for this change was discussed here: http://lists.llvm.org/pipermail/llvm-dev/2016-September/105373.html http://lists.llvm.org/pipermail/llvm-dev/2017-July/114885.html Alive proofs for the new bit magic: https://rise4fun.com/Alive/XG7 Differential Revision: https://reviews.llvm.org/D46086 llvm-svn: 331486
* GlobalISel: Use a callback to compute constrained reg class for unallocatble ↵Tom Stellard2018-05-031-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | registers Summary: constrainOperandRegClass() currently fails if it tries to constrain the register class of an operand that is defeined with an unallocatable register class. This patch resolves this by adding a target callback to compute register constriants in this case. This is required by the AMDGPU because many of its instructions have source opreands defined with the unallocatable register classe VS_32 which is a union of two allocatable register classes VGPR_32 and SReg_32. Reviewers: dsanders, aditya_nandakumar Reviewed By: aditya_nandakumar Subscribers: rovka, kristof.beyls, tpr, llvm-commits Differential Revision: https://reviews.llvm.org/D45991 llvm-svn: 331485
* [ThinLTO] Add support for optimization remarks to thinBackendTeresa Johnson2018-05-031-15/+20
| | | | | | | | | | | | | | Summary: Support was added to the regular LTO backend, but not thinBackend. This patch adds that support. Reviewers: pcc, davide Subscribers: mehdi_amini, inglorion, llvm-commits Differential Revision: https://reviews.llvm.org/D46376 llvm-svn: 331481
* [X86][AVX512] VPLZCNT instructions match SchedWriteVecIMul scheduling class ↵Simon Pilgrim2018-05-032-17/+4
| | | | | | not SchedWriteVecALU. llvm-svn: 331473
* [X86] Split WriteVecShift/WriteVarVecShift into MMX, XMM and YMM/ZMM ↵Simon Pilgrim2018-05-0314-597/+170
| | | | | | | | scheduler classes This took a bit of extra work as on Intel targets the old (V)PSLLDrr/(V)PSLLDrm style instructions act differently - I ended up creating WriteVecShiftImm classes for XMM/YMM/ZMM vector shift by immediate and retaining WriteVecShift as the default (used only by MMX) plus WriteVecShiftX/WriteVecShiftY. X86SchedWriteWidths hides most of this thank goodness. llvm-svn: 331472
* [DebugInfo] Correction for an assert in DIExpression::createFragmentExpressionBjorn Pettersson2018-05-031-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When we create a fragment expression, and there already is an old fragment expression, we assert that the new fragment is within the range for the old fragment. If for example the old fragment expression says that we describe bit 10-16 of a variable (Offset=10, Size=6), and we now want to create a new fragment expression only describing bit 3-6 of the original value, then the resulting fragment expression should have Offset=13, Size=3. The assert is supposed to catch if the resulting fragment expression is outside the range for the old fragment. However, it used to verify that the Offset+Size of the new fragment was smaller or equal than Offset+Size for the old fragment. What we really want to check is that Offset+Size of the new fragment is smaller than the Size of the old fragment. Reviewers: aprantl, vsk Reviewed By: aprantl Subscribers: davide, llvm-commits, JDevlieghere Differential Revision: https://reviews.llvm.org/D46391 llvm-svn: 331465
* Reapply "[SelectionDAG] Selection of DBG_VALUE using a PHI node result (pt 2)"Bjorn Pettersson2018-05-032-6/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This reverts SVN r331441 (reapplies r331337), together with a fix in to handle an already existing fragment expression in the dbg.value that must be fragmented due to a split PHI node. This should solve the problem seen in PR37321, which was the reason for the revert of r331337. The situation in PR37321 is that we have a PHI node like this %u.sroa = phi i80 [ %u.sroa.x, %if.x ], [ %u.sroa.y, %if.y ], [ %u.sroa.z, %if.z ] and a dbg.value like this call void @llvm.dbg.value(metadata i80 %u.sroa, metadata !13, metadata !DIExpression(DW_OP_LLVM_fragment, 0, 80)) The phi node is split into three 32-bit PHI nodes %30:gr32 = PHI %11:gr32, %bb.4, %14:gr32, %bb.5, %27:gr32, %bb.8 %31:gr32 = PHI %12:gr32, %bb.4, %15:gr32, %bb.5, %28:gr32, %bb.8 %32:gr32 = PHI %13:gr32, %bb.4, %16:gr32, %bb.5, %29:gr32, %bb.8 but since the original value only is 80 bits we need to adjust the size of the last fragment expression, and with this patch we get DBG_VALUE debug-use %30:gr32, debug-use $noreg, !"u", !DIExpression(DW_OP_LLVM_fragment, 0, 32) DBG_VALUE debug-use %31:gr32, debug-use $noreg, !"u", !DIExpression(DW_OP_LLVM_fragment, 32, 32) DBG_VALUE debug-use %32:gr32, debug-use $noreg, !"u", !DIExpression(DW_OP_LLVM_fragment, 64, 16) Reviewers: vsk, aprantl, mstorsjo Reviewed By: aprantl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D46384 llvm-svn: 331464
* [X86] Split WriteVecALU/WritePHAdd into XMM and YMM/ZMM scheduler classesSimon Pilgrim2018-05-0311-754/+90
| | | | llvm-svn: 331453
* ARM: don't try to over-align large vectors as arguments.Tim Northover2018-05-032-0/+16
| | | | | | | | | | | | By default LLVM thinks very large vectors get aligned to their size when passed across functions. Unfortunately no-one told the ARM backend so it doesn't trigger stack realignment and so accesses can cause the usual misalignment issues (e.g. a data abort). This changes the ABI alignment to the stack alignment, which in practice (and as a bonus) also coincides with the alignment "natural" vectors get. llvm-svn: 331451
* perform DSE through launder.invariant.groupPiotr Padlewski2018-05-031-5/+5
| | | | | | | | | | | | | | | | | Summary: Alias Analysis knows that llvm.launder.invariant.group returns pointer that mustalias argument, but this information wasn't used, therefor we didn't DSE through launder.invariant.group Reviewers: chandlerc, dberlin, bogner, hfinkel, efriedma Reviewed By: dberlin Subscribers: amharc, llvm-commits, nlewycky, rsmith Differential Revision: https://reviews.llvm.org/D31581 llvm-svn: 331449
* Rename invariant.group.barrier to launder.invariant.groupPiotr Padlewski2018-05-038-21/+29
| | | | | | | | | | | | | | Summary: This is one of the initial commit of "RFC: Devirtualization v2" proposal: https://docs.google.com/document/d/16GVtCpzK8sIHNc2qZz6RN8amICNBtvjWUod2SujZVEo/edit?usp=sharing Reviewers: rsmith, amharc, kuhar, sanjoy Subscribers: arsenm, nhaehnle, javed.absar, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D45111 llvm-svn: 331448
* [X86][AVX512] VPAVG instructions should be tagged as SchedWriteVecALUSimon Pilgrim2018-05-031-1/+1
| | | | llvm-svn: 331446
* [X86] Split WriteVecIMul/WriteVecPMULLD/WriteMPSAD/WritePSADBW into XMM and ↵Simon Pilgrim2018-05-0311-261/+94
| | | | | | | | YMM/ZMM scheduler classes Also retagged VDBPSADBW instructions as SchedWritePSADBW instead of SchedWriteVecIMul which matches the behaviour on SkylakeServer (the only thing that supports it...) llvm-svn: 331445
* [X86] Update MMX instructions to be tagged with X86SchedWriteWidths typesSimon Pilgrim2018-05-032-77/+84
| | | | llvm-svn: 331443
* Revert "[SelectionDAG] Selection of DBG_VALUE using a PHI node result (pt 2)"Martin Storsjo2018-05-032-36/+6
| | | | | | | This reverts SVN r331337, see PR37321 for details on the regression it introduced. llvm-svn: 331441
* [TableGen][NFC] Make ResourceCycles definitions more explicit.Clement Courbet2018-05-033-12/+12
| | | | | | https://reviews.llvm.org/D46356 llvm-svn: 331439
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