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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-05-03 18:22:49 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-05-03 18:22:49 +0000 |
| commit | 0720c8d90eb4938450ff3924a7f4e9f01c61d57c (patch) | |
| tree | 47260f76b06474e28fc9c9b16939510c704fa687 /llvm/lib | |
| parent | f2d2cedab48f07d63b219836fcb7b653c9aeb27b (diff) | |
| download | bcm5719-llvm-0720c8d90eb4938450ff3924a7f4e9f01c61d57c.tar.gz bcm5719-llvm-0720c8d90eb4938450ff3924a7f4e9f01c61d57c.zip | |
[X86][AVX512] VPLZCNT instructions match SchedWriteVecIMul scheduling class not SchedWriteVecALU.
llvm-svn: 331473
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 3 | ||||
| -rwxr-xr-x | llvm/lib/Target/X86/X86SchedSkylakeServer.td | 18 |
2 files changed, 4 insertions, 17 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index 23bc1d83acf..537e3f08835 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -9842,9 +9842,8 @@ multiclass avx512_unary_lowering<string InstrStr, SDNode OpNode, } } -// FIXME: Is there a better scheduler class for VPLZCNT? defm VPLZCNT : avx512_unary_rm_vl_dq<0x44, 0x44, "vplzcnt", ctlz, - SchedWriteVecALU, HasCDI>; + SchedWriteVecIMul, HasCDI>; // FIXME: Is there a better scheduler class for VPCONFLICT? defm VPCONFLICT : avx512_unary_rm_vl_dq<0xC4, 0xC4, "vpconflict", X86Conflict, diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td index 41b75824777..6c978144ee2 100755 --- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td @@ -1249,13 +1249,7 @@ def: InstRW<[SKXWriteResGroup50], (instregex "VCVTDQ2PSYrr", "VCVTUDQ2PSZrr", "VCVTUQQ2PDZ128rr", "VCVTUQQ2PDZ256rr", - "VCVTUQQ2PDZrr", - "VPLZCNTDZ128rr", - "VPLZCNTDZ256rr", - "VPLZCNTDZrr", - "VPLZCNTQZ128rr", - "VPLZCNTQZ256rr", - "VPLZCNTQZrr")>; + "VCVTUQQ2PDZrr")>; def SKXWriteResGroup51 : SchedWriteRes<[SKXPort5]> { let Latency = 4; @@ -2681,9 +2675,7 @@ def: InstRW<[SKXWriteResGroup149], (instregex "CVTDQ2PSrm", "VCVTUDQ2PDZ128rm(b?)", "VCVTUDQ2PSZ128rm(b?)", "VCVTUQQ2PDZ128rm(b?)", - "VCVTUQQ2PSZ128rm(b?)", - "VPLZCNTDZ128rm(b?)", - "VPLZCNTQZ128rm(b?)")>; + "VCVTUQQ2PSZ128rm(b?)")>; def SKXWriteResGroup151 : SchedWriteRes<[SKXPort5,SKXPort23]> { let Latency = 10; @@ -2807,11 +2799,7 @@ def: InstRW<[SKXWriteResGroup161], (instregex "VCVTDQ2PDZ256rm(b?)", "VCVTUDQ2PSZrm(b?)", "VCVTUQQ2PDZ256rm(b?)", "VCVTUQQ2PDZrm(b?)", - "VCVTUQQ2PSZ256rm(b?)", - "VPLZCNTDZ256rm(b?)", - "VPLZCNTDZrm(b?)", - "VPLZCNTQZ256rm(b?)", - "VPLZCNTQZrm(b?)")>; + "VCVTUQQ2PSZ256rm(b?)")>; def SKXWriteResGroup162 : SchedWriteRes<[SKXPort5,SKXPort23]> { let Latency = 11; |
